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Searched refs:MAX_INPUT_FREQ (Results 1 – 1 of 1) sorted by relevance

/drivers/clk/analogbits/
Dwrpll-cln28hpc.c34 #define MAX_INPUT_FREQ 600000000 macro
188 if (parent_rate > MAX_INPUT_FREQ || parent_rate < MIN_POST_DIVR_FREQ) in __wrpll_update_parent_rate()