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Searched refs:MUX_F (Results 1 – 11 of 11) sorted by relevance

/drivers/clk/samsung/
Dclk-exynos5420.c493 MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p,
503 MUX_F(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p,
574 MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2,
603 MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
606 MUX_F(CLK_MOUT_KPLL, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
618 MUX_F(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1,
661 MUX_F(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p,
671 MUX_F(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1,
676 MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1,
716 MUX_F(CLK_MOUT_SW_ACLK_G3D, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p,
[all …]
Dclk-exynos7.c726 MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_user_p,
728 MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_user_p,
730 MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_user_p,
732 MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_user_p,
734 MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_user_p,
Dclk-exynos4.c420 MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
425 MUX_F(CLK_MOUT_G3D1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1,
427 MUX_F(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1,
476 MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1,
553 MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1,
Dclk.h144 #define MUX_F(_id, cname, pnames, o, s, w, f, mf) \ macro
Dclk-exynos3250.c320 MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1,
322 MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
Dclk-s3c64xx.c125 MUX_F(0, "mout_syncmux", hclkx2_p, OTHERS, 6, 1, 0, CLK_MUX_READ_ONLY),
Dclk-exynos5433.c3284 MUX_F(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p,
3286 MUX_F(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
3572 MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p,
3581 MUX_F(CLK_MOUT_APOLLO, "mout_apollo", mout_apollo_p, MUX_SEL_APOLLO2,
3798 MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p,
3807 MUX_F(CLK_MOUT_ATLAS, "mout_atlas", mout_atlas_p, MUX_SEL_ATLAS2,
Dclk-s5pv210.c369 MUX_F(FIN_PLL, "fin_pll", fin_pll_p, OM_STAT, 0, 1,
Dclk-exynos5250.c256 MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
/drivers/clk/zte/
Dclk.h98 #define MUX_F(_id, _name, _parent, _reg, _shift, _width, _flag, _mflag) \ macro
115 MUX_F(_id, _name, _parent, _reg, _shift, _width, 0, 0)
Dclk-zx296718.c464 MUX_F(0, "a53_mux", a53_coreclk_p, TOP_CLK_MUX0, 0, 3, CLK_SET_RATE_PARENT, 0),
473 MUX_F(0, "wdt_mux", wdt_ares_p, TOP_CLK_MUX9, 8, 1, CLK_SET_RATE_PARENT, 0),
482 MUX_F(0, "vou_main_w_mux", vou_main_wclk_p, TOP_CLK_MUX7, 4, 3, CLK_SET_RATE_PARENT, 0),
483 MUX_F(0, "vou_aux_w_mux", vou_aux_wclk_p, TOP_CLK_MUX7, 8, 3, CLK_SET_RATE_PARENT, 0),