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Searched refs:PA_CL_CLIP_CNTL__UCP_ENA_0_MASK (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h5582 #define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x00000001L macro
Dgfx_7_2_sh_mask.h5565 #define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x1 macro
Dgfx_8_0_sh_mask.h6353 #define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x1 macro
Dgfx_8_1_sh_mask.h6887 #define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x1 macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h16908 #define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK … macro
Dgc_9_1_sh_mask.h18217 #define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK … macro
Dgc_9_2_1_sh_mask.h18093 #define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK … macro
Dgc_10_3_0_sh_mask.h22516 #define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK … macro
Dgc_10_1_0_sh_mask.h24281 #define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK … macro