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Searched refs:PA_CL_CLIP_CNTL__UCP_ENA_2_MASK (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h5586 #define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x00000004L macro
Dgfx_7_2_sh_mask.h5569 #define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x4 macro
Dgfx_8_0_sh_mask.h6357 #define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x4 macro
Dgfx_8_1_sh_mask.h6891 #define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x4 macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h16910 #define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK … macro
Dgc_9_1_sh_mask.h18219 #define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK … macro
Dgc_9_2_1_sh_mask.h18095 #define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK … macro
Dgc_10_3_0_sh_mask.h22518 #define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK … macro
Dgc_10_1_0_sh_mask.h24283 #define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK … macro