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Searched refs:PA_CL_CLIP_CNTL__UCP_ENA_5_MASK (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h5592 #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x00000020L macro
Dgfx_7_2_sh_mask.h5575 #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x20 macro
Dgfx_8_0_sh_mask.h6363 #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x20 macro
Dgfx_8_1_sh_mask.h6897 #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x20 macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h16913 #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK … macro
Dgc_9_1_sh_mask.h18222 #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK … macro
Dgc_9_2_1_sh_mask.h18098 #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK … macro
Dgc_10_3_0_sh_mask.h22521 #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK … macro
Dgc_10_1_0_sh_mask.h24286 #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK … macro