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Searched refs:PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dgfx_v6_0.c1776 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT)); in gfx_v6_0_constants_init()
Dgfx_v7_0.c2039 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT)); in gfx_v7_0_constants_init()
/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h5617 #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x00000001 macro
Dgfx_7_2_sh_mask.h5670 #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1 macro
Dgfx_8_0_sh_mask.h6458 #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1 macro
Dgfx_8_1_sh_mask.h6992 #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1 macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h1630 #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT … macro
Dgc_9_1_sh_mask.h1493 #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT … macro
Dgc_9_2_1_sh_mask.h1456 #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT … macro
Dgc_10_3_0_sh_mask.h7452 #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT … macro
Dgc_10_1_0_sh_mask.h7150 #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT … macro