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Searched refs:PA_CL_UCP_5_X__DATA_REGISTER_MASK (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h5712 #define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xffffffffL macro
Dgfx_7_2_sh_mask.h5651 #define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xffffffff macro
Dgfx_8_0_sh_mask.h6439 #define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xffffffff macro
Dgfx_8_1_sh_mask.h6973 #define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xffffffff macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h15520 #define PA_CL_UCP_5_X__DATA_REGISTER_MASK … macro
Dgc_9_1_sh_mask.h16829 #define PA_CL_UCP_5_X__DATA_REGISTER_MASK … macro
Dgc_9_2_1_sh_mask.h16701 #define PA_CL_UCP_5_X__DATA_REGISTER_MASK … macro
Dgc_10_3_0_sh_mask.h21053 #define PA_CL_UCP_5_X__DATA_REGISTER_MASK … macro
Dgc_10_1_0_sh_mask.h22899 #define PA_CL_UCP_5_X__DATA_REGISTER_MASK … macro