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Searched refs:PIPECONF_ENABLE (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/i915/gvt/
Ddisplay.c62 if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE)) in edp_pipe_is_enabled()
78 if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE) in pipe_is_enabled()
186 ~(PIPECONF_ENABLE | I965_PIPECONF_ACTIVE); in emulate_monitor_status_change()
246 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; in emulate_monitor_status_change()
504 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; in emulate_monitor_status_change()
Dhandlers.c454 if (data & PIPECONF_ENABLE) in pipeconf_mmio_write()
/drivers/video/fbdev/intelfb/
Dintelfbhw.h286 #define PIPECONF_ENABLE (1 << 31) macro
Dintelfbhw.c1354 tmp &= ~PIPECONF_ENABLE; in intelfbhw_program_mode()
1366 tmp &= ~PIPECONF_ENABLE; in intelfbhw_program_mode()
1441 OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE); in intelfbhw_program_mode()
/drivers/gpu/drm/i915/display/
Dicl_dsi.c997 tmp |= PIPECONF_ENABLE; in gen11_dsi_enable_transcoder()
1223 tmp &= ~PIPECONF_ENABLE; in gen11_dsi_disable_transcoder()
1628 ret = tmp & PIPECONF_ENABLE; in gen11_dsi_get_hw_state()
Dintel_display_power.c1248 if ((intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1250 if ((intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1264 return intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE && in i830_pipes_power_well_enabled()
1265 intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in i830_pipes_power_well_enabled()
Dintel_display.c1281 cur_state = !!(val & PIPECONF_ENABLE); in assert_pipe()
1884 if (val & PIPECONF_ENABLE) { in intel_enable_pipe()
1890 intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE); in intel_enable_pipe()
1925 if ((val & PIPECONF_ENABLE) == 0) in intel_disable_pipe()
1937 val &= ~PIPECONF_ENABLE; in intel_disable_pipe()
1940 if ((val & PIPECONF_ENABLE) == 0) in intel_disable_pipe()
8985 pipeconf |= intel_de_read(dev_priv, PIPECONF(crtc->pipe)) & PIPECONF_ENABLE; in i9xx_set_pipeconf()
9481 if (!(tmp & PIPECONF_ENABLE)) in i9xx_get_pipe_config()
10718 if (!(tmp & PIPECONF_ENABLE)) in ilk_get_pipe_config()
11068 return tmp & PIPECONF_ENABLE; in hsw_get_transcoder_state()
[all …]
Dvlv_dsi.c1035 enabled = intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in intel_dsi_get_hw_state()
Dintel_dp.c5528 trans_conf_value &= ~PIPECONF_ENABLE; in intel_dp_autotest_phy_ddi_disable()
5555 trans_conf_value |= PIPECONF_ENABLE; in intel_dp_autotest_phy_ddi_enable()
/drivers/gpu/drm/i915/
Di915_reg.h5884 #define PIPECONF_ENABLE (1 << 31) macro