Searched refs:PIPESRC (Results 1 – 4 of 4) sorted by relevance
| /drivers/gpu/drm/i915/gvt/ |
| D | fb_decoder.c | 263 plane->width = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >> in intel_vgpu_decode_primary_plane()
266 plane->height = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & in intel_vgpu_decode_primary_plane()
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| D | handlers.c | 2171 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL); in init_generic_mmio_info()
2181 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL); in init_generic_mmio_info()
2191 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL); in init_generic_mmio_info()
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| /drivers/gpu/drm/i915/display/ |
| D | intel_display.c | 8875 intel_de_write(dev_priv, PIPESRC(pipe), in intel_set_pipe_src_size()
8946 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe)); in intel_get_pipe_src_size()
9367 val = intel_de_read(dev_priv, PIPESRC(pipe)); in i9xx_get_initial_plane_config()
18099 intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1)); in i830_enable_pipe()
19057 error->pipe[i].source = intel_de_read(dev_priv, PIPESRC(i)); in intel_display_capture_error_state()
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| /drivers/gpu/drm/i915/ |
| D | i915_reg.h | 4343 #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC) macro
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