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Searched refs:PIPE_A (Results 1 – 25 of 30) sorted by relevance

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/drivers/gpu/drm/i915/gvt/
Dhandlers.c2035 MMIO_D(PIPEDSL(PIPE_A), D_ALL); in init_generic_mmio_info()
2040 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
2045 MMIO_D(PIPESTAT(PIPE_A), D_ALL); in init_generic_mmio_info()
2050 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL); in init_generic_mmio_info()
2055 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL); in init_generic_mmio_info()
2060 MMIO_D(CURCNTR(PIPE_A), D_ALL); in init_generic_mmio_info()
2064 MMIO_D(CURPOS(PIPE_A), D_ALL); in init_generic_mmio_info()
2068 MMIO_D(CURBASE(PIPE_A), D_ALL); in init_generic_mmio_info()
2072 MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL); in init_generic_mmio_info()
2085 MMIO_D(DSPCNTR(PIPE_A), D_ALL); in init_generic_mmio_info()
[all …]
Ddisplay.c46 pipe = PIPE_A; in get_edp_pipe()
75 pipe < PIPE_A || pipe >= I915_MAX_PIPES)) in pipe_is_enabled()
246 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; in emulate_monitor_status_change()
247 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= I965_PIPECONF_ACTIVE; in emulate_monitor_status_change()
504 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; in emulate_monitor_status_change()
595 [PIPE_A] = PIPE_A_VBLANK, in emulate_vblank_on_pipe()
601 if (pipe < PIPE_A || pipe > PIPE_C) in emulate_vblank_on_pipe()
Dreg.h72 (((p) == PIPE_A) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50080)) : \
82 (((reg) == 0x50080 || (reg) == 0x50090) ? (PIPE_A) : \
Dcmd_parser.c1252 [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE}, in gen8_decode_mi_display_flip()
1254 [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE}, in gen8_decode_mi_display_flip()
1307 info->pipe = PIPE_A; in skl_decode_mi_display_flip()
1320 info->pipe = PIPE_A; in skl_decode_mi_display_flip()
Dinterrupt.c453 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_a, GEN8_DE_PIPE_ISR(PIPE_A));
/drivers/gpu/drm/i915/
Di915_pci.c99 [PIPE_A] = CURSOR_A_OFFSET, \
104 [PIPE_A] = CURSOR_A_OFFSET, \
110 [PIPE_A] = CURSOR_A_OFFSET, \
117 [PIPE_A] = CURSOR_A_OFFSET, \
124 [PIPE_A] = CURSOR_A_OFFSET, \
162 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
183 .pipe_mask = BIT(PIPE_A), \
225 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
315 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
368 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
[all …]
Dintel_pm.c495 case PIPE_A: in vlv_get_fifo_size()
982 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); in g4x_write_wm_values()
988 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | in g4x_write_wm_values()
989 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); in g4x_write_wm_values()
1032 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); in vlv_write_wm_values()
1034 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) | in vlv_write_wm_values()
1035 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | in vlv_write_wm_values()
1036 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); in vlv_write_wm_values()
1058 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) | in vlv_write_wm_values()
1059 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) | in vlv_write_wm_values()
[all …]
Dintel_device_info.c399 runtime->num_scalers[PIPE_A] = 2; in intel_device_info_runtime_init()
425 runtime->num_sprites[PIPE_A] = 2; in intel_device_info_runtime_init()
467 info->pipe_mask &= ~BIT(PIPE_A); in intel_device_info_runtime_init()
Di915_trace.h44 __entry->frame[PIPE_A], __entry->scanline[PIPE_A],
71 __entry->frame[PIPE_A], __entry->scanline[PIPE_A],
168 __entry->frame[PIPE_A], __entry->scanline[PIPE_A],
Di915_irq.c557 i915_enable_pipestat(dev_priv, PIPE_A, in i915_enable_asle_pipestat()
1332 case PIPE_A: in i9xx_pipestat_irq_ack()
1760 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); in ibx_irq_handler()
2772 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in vlv_display_irq_postinstall()
3568 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
3744 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
3861 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in i965_irq_postinstall()
3862 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
/drivers/gpu/drm/i915/display/
Dintel_ddi.c1400 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), in hsw_fdi_link_train()
1407 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
1408 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
1413 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
1441 intel_de_write(dev_priv, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); in hsw_fdi_link_train()
1445 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
1446 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
1452 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
1454 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp); in hsw_fdi_link_train()
1455 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
[all …]
Dintel_crt.c238 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in hsw_disable_crt()
267 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in hsw_post_disable_crt()
279 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in hsw_pre_pll_enable_crt()
324 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in hsw_enable_crt()
1045 crt->base.pipe_mask = BIT(PIPE_A); in intel_crt_init()
1106 FDI_RX_CTL(PIPE_A)) & fdi_config; in intel_crt_init()
Dintel_pipe_crc.c179 case PIPE_A: in vlv_pipe_crc_ctl_reg()
243 case PIPE_A: in vlv_undo_pipe_scramble_reset()
316 pipe_config->hw.active && crtc->pipe == PIPE_A && in intel_crtc_crc_setup_workarounds()
Dintel_fifo_underrun.c135 u32 bit = (pipe == PIPE_A) ? in ilk_set_fifo_underrun_reporting()
203 u32 bit = (pch_transcoder == PIPE_A) ? in ibx_set_fifo_underrun_reporting()
Dintel_vdsc.c351 (pipe != PIPE_A || in intel_dsc_source_support()
375 drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A); in is_pipe_dsc()
485 if (INTEL_GEN(i915) >= 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A) in intel_dsc_power_domain()
Dintel_display_power.c1248 if ((intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1249 i830_enable_pipe(dev_priv, PIPE_A); in i830_pipes_power_well_enable()
1258 i830_disable_pipe(dev_priv, PIPE_A); in i830_pipes_power_well_disable()
1264 return intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE && in i830_pipes_power_well_enabled()
1407 if (pipe != PIPE_A) in vlv_display_power_well_init()
1631 pipe = PIPE_A; in chv_dpio_cmn_power_well_enable()
1695 assert_pll_disabled(dev_priv, PIPE_A); in chv_dpio_cmn_power_well_disable()
1721 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; in assert_chv_phy_powergate()
1850 enum pipe pipe = PIPE_A; in chv_pipe_power_well_enabled()
1881 enum pipe pipe = PIPE_A; in chv_set_pipe_power_well()
[all …]
Dintel_display.h86 PIPE_A = 0, enumerator
105 TRANSCODER_A = PIPE_A,
Dintel_dp.c872 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); in vlv_find_free_pps()
929 pipe = PIPE_A; in vlv_power_sequencer_pipe()
1006 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { in vlv_initial_pps_pipe()
3568 *pipe = PIPE_A; in cpt_dp_port_selected()
3997 if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B)) in vlv_detach_power_sequencer()
4575 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_dp_link_down()
4576 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_dp_link_down()
4580 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) | in intel_dp_link_down()
4589 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); in intel_dp_link_down()
4590 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_dp_link_down()
[all …]
Dintel_display.c1476 if (pipe != PIPE_A) { in chv_enable_pll()
1583 if (pipe != PIPE_A) in vlv_disable_pll()
1600 if (pipe != PIPE_A) in chv_disable_pll()
1724 assert_fdi_rx_enabled(dev_priv, PIPE_A); in lpt_enable_pch_transcoder()
1726 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); in lpt_enable_pch_transcoder()
1732 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val); in lpt_enable_pch_transcoder()
1793 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); in lpt_disable_pch_transcoder()
1795 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val); in lpt_disable_pch_transcoder()
1803 return PIPE_A; in intel_crtc_pch_transcoder()
5806 case PIPE_A: in ivb_update_fdi_bc_bifurcation()
[all …]
Dintel_hdmi.c2093 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_hdmi()
2094 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_hdmi()
2097 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); in intel_disable_hdmi()
2111 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); in intel_disable_hdmi()
2112 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_hdmi()
2113 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_hdmi()
3414 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in intel_hdmi_init()
Dintel_sdvo.c1786 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_sdvo()
1787 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_sdvo()
1790 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); in intel_disable_sdvo()
1796 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); in intel_disable_sdvo()
1797 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_sdvo()
1798 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_sdvo()
Dvlv_dsi.c1060 *pipe = port == PORT_A ? PIPE_A : PIPE_B; in intel_dsi_get_hw_state()
1871 intel_encoder->pipe_mask = BIT(PIPE_A); in vlv_dsi_init()
Dicl_dsi.c796 case PIPE_A: in gen11_dsi_configure_transcoder()
1611 *pipe = PIPE_A; in gen11_dsi_get_hw_state()
/drivers/video/fbdev/intelfb/
Dintelfbhw.c482 if (unlikely(pipe == PIPE_A)) in intelfbhw_active_pipe()
483 return PIPE_A; in intelfbhw_active_pipe()
488 if (likely(pipe == PIPE_A)) in intelfbhw_active_pipe()
489 return PIPE_A; in intelfbhw_active_pipe()
494 pipe = PIPE_A; in intelfbhw_active_pipe()
503 u32 palette_reg = (dinfo->pipe == PIPE_A) ? in intelfbhw_setcolreg()
Dintelfbhw.h182 #define PIPE_A 0 macro

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