Searched refs:PLL_35XX_RATE (Results 1 – 7 of 7) sorted by relevance
| /drivers/clk/samsung/ |
| D | clk-exynos5420.c | 1400 PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0),
1401 PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0),
1402 PLL_35XX_RATE(24 * MHZ, 1800000000, 225, 3, 0),
1403 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
1404 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
1405 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
1406 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
1407 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
1408 PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 2, 1),
1409 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
[all …]
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| D | clk-exynos5260.c | 23 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
24 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
25 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
26 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
27 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
28 PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
29 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
30 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
31 PLL_35XX_RATE(24 * MHZ, 933000000, 311, 4, 1),
32 PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),
[all …]
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| D | clk-exynos5250.c | 714 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
715 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
716 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
717 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
718 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
719 PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 4, 0),
720 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 6, 0),
721 PLL_35XX_RATE(24 * MHZ, 1000000000, 125, 3, 0),
722 PLL_35XX_RATE(24 * MHZ, 900000000, 150, 4, 0),
723 PLL_35XX_RATE(24 * MHZ, 800000000, 100, 3, 0),
[all …]
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| D | clk-exynos3250.c | 670 PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
671 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
672 PLL_35XX_RATE(24 * MHZ, 1066000000, 533, 6, 1),
673 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
674 PLL_35XX_RATE(24 * MHZ, 960000000, 320, 4, 1),
675 PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),
676 PLL_35XX_RATE(24 * MHZ, 850000000, 425, 6, 1),
677 PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),
678 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
679 PLL_35XX_RATE(24 * MHZ, 667000000, 667, 12, 1),
[all …]
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| D | clk-exynos4.c | 1104 PLL_35XX_RATE(24 * MHZ, 1704000000, 213, 3, 0),
1105 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
1106 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
1107 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
1108 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
1109 PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 4, 0),
1110 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 6, 0),
1111 PLL_35XX_RATE(24 * MHZ, 1000000000, 125, 3, 0),
1112 PLL_35XX_RATE(24 * MHZ, 900000000, 150, 4, 0),
1113 PLL_35XX_RATE(24 * MHZ, 800000000, 100, 3, 0),
[all …]
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| D | clk-exynos5433.c | 715 PLL_35XX_RATE(24 * MHZ, 2500000000U, 625, 6, 0),
716 PLL_35XX_RATE(24 * MHZ, 2400000000U, 500, 5, 0),
717 PLL_35XX_RATE(24 * MHZ, 2300000000U, 575, 6, 0),
718 PLL_35XX_RATE(24 * MHZ, 2200000000U, 550, 6, 0),
719 PLL_35XX_RATE(24 * MHZ, 2100000000U, 350, 4, 0),
720 PLL_35XX_RATE(24 * MHZ, 2000000000U, 500, 6, 0),
721 PLL_35XX_RATE(24 * MHZ, 1900000000U, 475, 6, 0),
722 PLL_35XX_RATE(24 * MHZ, 1800000000U, 375, 5, 0),
723 PLL_35XX_RATE(24 * MHZ, 1700000000U, 425, 6, 0),
724 PLL_35XX_RATE(24 * MHZ, 1600000000U, 400, 6, 0),
[all …]
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| D | clk-pll.h | 46 #define PLL_35XX_RATE(_fin, _rate, _m, _p, _s) \ macro
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