Searched refs:PLL_REF_DIV (Results 1 – 5 of 5) sorted by relevance
| /drivers/clk/x86/ |
| D | clk-cgu-pll.c | 18 #define PLL_REF_DIV(x) ((x) + 0x08) macro
45 mult = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 0, 12); in lgm_pll_recalc_rate()
46 div = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 18, 6); in lgm_pll_recalc_rate()
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_clock_source.h | 52 CS_SF(PLL_REF_DIV, PLL_REF_DIV, mask_sh)
148 type PLL_REF_DIV; \
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| D | dce_clock_source.c | 1447 calc_pll_cs_init_data.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV; in dce110_clk_src_construct()
1466 calc_pll_cs_init_data_hdmi.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV; in dce110_clk_src_construct()
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| /drivers/video/fbdev/aty/ |
| D | mach64_ct.c | 388 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par); in aty_get_pll_ct()
514 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par); in aty_init_pll_ct()
627 aty_st_pll_ct(PLL_REF_DIV, pll->ct.pll_ref_div, par); in aty_resume_pll_ct()
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| D | atyfb_base.c | 2465 u8 pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par); in aty_init()
3095 M = pll_regs[PLL_REF_DIV]; in atyfb_setup_sparc()
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