1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Universal Flash Storage Host controller driver
4 * Copyright (C) 2011-2013 Samsung India Software Operations
5 *
6 * Authors:
7 * Santosh Yaraganavi <santosh.sy@samsung.com>
8 * Vinayak Holikatti <h.vinayak@samsung.com>
9 */
10
11 #ifndef _UFSHCI_H
12 #define _UFSHCI_H
13
14 enum {
15 TASK_REQ_UPIU_SIZE_DWORDS = 8,
16 TASK_RSP_UPIU_SIZE_DWORDS = 8,
17 ALIGNED_UPIU_SIZE = 512,
18 };
19
20 /* UFSHCI Registers */
21 enum {
22 REG_CONTROLLER_CAPABILITIES = 0x00,
23 REG_UFS_VERSION = 0x08,
24 REG_CONTROLLER_DEV_ID = 0x10,
25 REG_CONTROLLER_PROD_ID = 0x14,
26 REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18,
27 REG_INTERRUPT_STATUS = 0x20,
28 REG_INTERRUPT_ENABLE = 0x24,
29 REG_CONTROLLER_STATUS = 0x30,
30 REG_CONTROLLER_ENABLE = 0x34,
31 REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
32 REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
33 REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
34 REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
35 REG_UIC_ERROR_CODE_DME = 0x48,
36 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
37 REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
38 REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
39 REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
40 REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
41 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
42 REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
43 REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
44 REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
45 REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
46 REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
47 REG_UIC_COMMAND = 0x90,
48 REG_UIC_COMMAND_ARG_1 = 0x94,
49 REG_UIC_COMMAND_ARG_2 = 0x98,
50 REG_UIC_COMMAND_ARG_3 = 0x9C,
51
52 UFSHCI_REG_SPACE_SIZE = 0xA0,
53
54 REG_UFS_CCAP = 0x100,
55 REG_UFS_CRYPTOCAP = 0x104,
56
57 UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400,
58 };
59
60 /* Controller capability masks */
61 enum {
62 MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F,
63 MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
64 MASK_AUTO_HIBERN8_SUPPORT = 0x00800000,
65 MASK_64_ADDRESSING_SUPPORT = 0x01000000,
66 MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
67 MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
68 MASK_CRYPTO_SUPPORT = 0x10000000,
69 };
70
71 #define UFS_MASK(mask, offset) ((mask) << (offset))
72
73 /* UFS Version 08h */
74 #define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0)
75 #define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16)
76
77 /*
78 * Controller UFSHCI version
79 * - 2.x and newer use the following scheme:
80 * major << 8 + minor << 4
81 * - 1.x has been converted to match this in
82 * ufshcd_get_ufs_version()
83 */
ufshci_version(u32 major,u32 minor)84 static inline u32 ufshci_version(u32 major, u32 minor)
85 {
86 return (major << 8) + (minor << 4);
87 }
88
89 /*
90 * HCDDID - Host Controller Identification Descriptor
91 * - Device ID and Device Class 10h
92 */
93 #define DEVICE_CLASS UFS_MASK(0xFFFF, 0)
94 #define DEVICE_ID UFS_MASK(0xFF, 24)
95
96 /*
97 * HCPMID - Host Controller Identification Descriptor
98 * - Product/Manufacturer ID 14h
99 */
100 #define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0)
101 #define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16)
102
103 /* AHIT - Auto-Hibernate Idle Timer */
104 #define UFSHCI_AHIBERN8_TIMER_MASK GENMASK(9, 0)
105 #define UFSHCI_AHIBERN8_SCALE_MASK GENMASK(12, 10)
106 #define UFSHCI_AHIBERN8_SCALE_FACTOR 10
107 #define UFSHCI_AHIBERN8_MAX (1023 * 100000)
108
109 /*
110 * IS - Interrupt Status - 20h
111 */
112 #define UTP_TRANSFER_REQ_COMPL 0x1
113 #define UIC_DME_END_PT_RESET 0x2
114 #define UIC_ERROR 0x4
115 #define UIC_TEST_MODE 0x8
116 #define UIC_POWER_MODE 0x10
117 #define UIC_HIBERNATE_EXIT 0x20
118 #define UIC_HIBERNATE_ENTER 0x40
119 #define UIC_LINK_LOST 0x80
120 #define UIC_LINK_STARTUP 0x100
121 #define UTP_TASK_REQ_COMPL 0x200
122 #define UIC_COMMAND_COMPL 0x400
123 #define DEVICE_FATAL_ERROR 0x800
124 #define CONTROLLER_FATAL_ERROR 0x10000
125 #define SYSTEM_BUS_FATAL_ERROR 0x20000
126 #define CRYPTO_ENGINE_FATAL_ERROR 0x40000
127
128 #define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\
129 UIC_HIBERNATE_EXIT)
130
131 #define UFSHCD_UIC_PWR_MASK (UFSHCD_UIC_HIBERN8_MASK |\
132 UIC_POWER_MODE)
133
134 #define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK)
135
136 #define UFSHCD_ERROR_MASK (UIC_ERROR | INT_FATAL_ERRORS)
137
138 #define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
139 CONTROLLER_FATAL_ERROR |\
140 SYSTEM_BUS_FATAL_ERROR |\
141 CRYPTO_ENGINE_FATAL_ERROR |\
142 UIC_LINK_LOST)
143
144 /* HCS - Host Controller Status 30h */
145 #define DEVICE_PRESENT 0x1
146 #define UTP_TRANSFER_REQ_LIST_READY 0x2
147 #define UTP_TASK_REQ_LIST_READY 0x4
148 #define UIC_COMMAND_READY 0x8
149 #define HOST_ERROR_INDICATOR 0x10
150 #define DEVICE_ERROR_INDICATOR 0x20
151 #define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
152
153 #define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\
154 UTP_TASK_REQ_LIST_READY |\
155 UIC_COMMAND_READY)
156
157 enum {
158 PWR_OK = 0x0,
159 PWR_LOCAL = 0x01,
160 PWR_REMOTE = 0x02,
161 PWR_BUSY = 0x03,
162 PWR_ERROR_CAP = 0x04,
163 PWR_FATAL_ERROR = 0x05,
164 };
165
166 /* HCE - Host Controller Enable 34h */
167 #define CONTROLLER_ENABLE 0x1
168 #define CONTROLLER_DISABLE 0x0
169 #define CRYPTO_GENERAL_ENABLE 0x2
170
171 /* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
172 #define UIC_PHY_ADAPTER_LAYER_ERROR 0x80000000
173 #define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F
174 #define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 0xF
175 #define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR 0x10
176
177 /* UECDL - Host UIC Error Code Data Link Layer 3Ch */
178 #define UIC_DATA_LINK_LAYER_ERROR 0x80000000
179 #define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0xFFFF
180 #define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP 0x2
181 #define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP 0x4
182 #define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP 0x8
183 #define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF 0x20
184 #define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000
185 #define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001
186 #define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002
187
188 /* UECN - Host UIC Error Code Network Layer 40h */
189 #define UIC_NETWORK_LAYER_ERROR 0x80000000
190 #define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7
191 #define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE 0x1
192 #define UIC_NETWORK_BAD_DEVICEID_ENC 0x2
193 #define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING 0x4
194
195 /* UECT - Host UIC Error Code Transport Layer 44h */
196 #define UIC_TRANSPORT_LAYER_ERROR 0x80000000
197 #define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F
198 #define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE 0x1
199 #define UIC_TRANSPORT_UNKNOWN_CPORTID 0x2
200 #define UIC_TRANSPORT_NO_CONNECTION_RX 0x4
201 #define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING 0x8
202 #define UIC_TRANSPORT_BAD_TC 0x10
203 #define UIC_TRANSPORT_E2E_CREDIT_OVERFOW 0x20
204 #define UIC_TRANSPORT_SAFETY_VALUE_DROPPING 0x40
205
206 /* UECDME - Host UIC Error Code DME 48h */
207 #define UIC_DME_ERROR 0x80000000
208 #define UIC_DME_ERROR_CODE_MASK 0x1
209
210 /* UTRIACR - Interrupt Aggregation control register - 0x4Ch */
211 #define INT_AGGR_TIMEOUT_VAL_MASK 0xFF
212 #define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8)
213 #define INT_AGGR_COUNTER_AND_TIMER_RESET 0x10000
214 #define INT_AGGR_STATUS_BIT 0x100000
215 #define INT_AGGR_PARAM_WRITE 0x1000000
216 #define INT_AGGR_ENABLE 0x80000000
217
218 /* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
219 #define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1
220
221 /* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
222 #define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
223
224 /* UICCMD - UIC Command */
225 #define COMMAND_OPCODE_MASK 0xFF
226 #define GEN_SELECTOR_INDEX_MASK 0xFFFF
227
228 #define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
229 #define RESET_LEVEL 0xFF
230
231 #define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
232 #define CONFIG_RESULT_CODE_MASK 0xFF
233 #define GENERIC_ERROR_CODE_MASK 0xFF
234
235 /* GenSelectorIndex calculation macros for M-PHY attributes */
236 #define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
237 #define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
238
239 #define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
240 ((sel) & 0xFFFF))
241 #define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
242 #define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
243 #define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
244
245 /* Link Status*/
246 enum link_status {
247 UFSHCD_LINK_IS_DOWN = 1,
248 UFSHCD_LINK_IS_UP = 2,
249 };
250
251 /* UIC Commands */
252 enum uic_cmd_dme {
253 UIC_CMD_DME_GET = 0x01,
254 UIC_CMD_DME_SET = 0x02,
255 UIC_CMD_DME_PEER_GET = 0x03,
256 UIC_CMD_DME_PEER_SET = 0x04,
257 UIC_CMD_DME_POWERON = 0x10,
258 UIC_CMD_DME_POWEROFF = 0x11,
259 UIC_CMD_DME_ENABLE = 0x12,
260 UIC_CMD_DME_RESET = 0x14,
261 UIC_CMD_DME_END_PT_RST = 0x15,
262 UIC_CMD_DME_LINK_STARTUP = 0x16,
263 UIC_CMD_DME_HIBER_ENTER = 0x17,
264 UIC_CMD_DME_HIBER_EXIT = 0x18,
265 UIC_CMD_DME_TEST_MODE = 0x1A,
266 };
267
268 /* UIC Config result code / Generic error code */
269 enum {
270 UIC_CMD_RESULT_SUCCESS = 0x00,
271 UIC_CMD_RESULT_INVALID_ATTR = 0x01,
272 UIC_CMD_RESULT_FAILURE = 0x01,
273 UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
274 UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
275 UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
276 UIC_CMD_RESULT_BAD_INDEX = 0x05,
277 UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
278 UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
279 UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
280 UIC_CMD_RESULT_BUSY = 0x09,
281 UIC_CMD_RESULT_DME_FAILURE = 0x0A,
282 };
283
284 #define MASK_UIC_COMMAND_RESULT 0xFF
285
286 #define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8)
287 #define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0)
288
289 /* Interrupt disable masks */
290 enum {
291 /* Interrupt disable mask for UFSHCI v1.0 */
292 INTERRUPT_MASK_ALL_VER_10 = 0x30FFF,
293 INTERRUPT_MASK_RW_VER_10 = 0x30000,
294
295 /* Interrupt disable mask for UFSHCI v1.1 */
296 INTERRUPT_MASK_ALL_VER_11 = 0x31FFF,
297
298 /* Interrupt disable mask for UFSHCI v2.1 */
299 INTERRUPT_MASK_ALL_VER_21 = 0x71FFF,
300 };
301
302 /* CCAP - Crypto Capability 100h */
303 union ufs_crypto_capabilities {
304 __le32 reg_val;
305 struct {
306 u8 num_crypto_cap;
307 u8 config_count;
308 u8 reserved;
309 u8 config_array_ptr;
310 };
311 };
312
313 enum ufs_crypto_key_size {
314 UFS_CRYPTO_KEY_SIZE_INVALID = 0x0,
315 UFS_CRYPTO_KEY_SIZE_128 = 0x1,
316 UFS_CRYPTO_KEY_SIZE_192 = 0x2,
317 UFS_CRYPTO_KEY_SIZE_256 = 0x3,
318 UFS_CRYPTO_KEY_SIZE_512 = 0x4,
319 };
320
321 enum ufs_crypto_alg {
322 UFS_CRYPTO_ALG_AES_XTS = 0x0,
323 UFS_CRYPTO_ALG_BITLOCKER_AES_CBC = 0x1,
324 UFS_CRYPTO_ALG_AES_ECB = 0x2,
325 UFS_CRYPTO_ALG_ESSIV_AES_CBC = 0x3,
326 };
327
328 /* x-CRYPTOCAP - Crypto Capability X */
329 union ufs_crypto_cap_entry {
330 __le32 reg_val;
331 struct {
332 u8 algorithm_id;
333 u8 sdus_mask; /* Supported data unit size mask */
334 u8 key_size;
335 u8 reserved;
336 };
337 };
338
339 #define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 7)
340 #define UFS_CRYPTO_KEY_MAX_SIZE 64
341 /* x-CRYPTOCFG - Crypto Configuration X */
342 union ufs_crypto_cfg_entry {
343 __le32 reg_val[32];
344 struct {
345 u8 crypto_key[UFS_CRYPTO_KEY_MAX_SIZE];
346 u8 data_unit_size;
347 u8 crypto_cap_idx;
348 u8 reserved_1;
349 u8 config_enable;
350 u8 reserved_multi_host;
351 u8 reserved_2;
352 u8 vsb[2];
353 u8 reserved_3[56];
354 };
355 };
356
357 /*
358 * Request Descriptor Definitions
359 */
360
361 /* Transfer request command type */
362 enum {
363 UTP_CMD_TYPE_SCSI = 0x0,
364 UTP_CMD_TYPE_UFS = 0x1,
365 UTP_CMD_TYPE_DEV_MANAGE = 0x2,
366 };
367
368 /* To accommodate UFS2.0 required Command type */
369 enum {
370 UTP_CMD_TYPE_UFS_STORAGE = 0x1,
371 };
372
373 enum {
374 UTP_SCSI_COMMAND = 0x00000000,
375 UTP_NATIVE_UFS_COMMAND = 0x10000000,
376 UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
377 UTP_REQ_DESC_INT_CMD = 0x01000000,
378 UTP_REQ_DESC_CRYPTO_ENABLE_CMD = 0x00800000,
379 };
380
381 /* UTP Transfer Request Data Direction (DD) */
382 enum {
383 UTP_NO_DATA_TRANSFER = 0x00000000,
384 UTP_HOST_TO_DEVICE = 0x02000000,
385 UTP_DEVICE_TO_HOST = 0x04000000,
386 };
387
388 /* Overall command status values */
389 enum utp_ocs {
390 OCS_SUCCESS = 0x0,
391 OCS_INVALID_CMD_TABLE_ATTR = 0x1,
392 OCS_INVALID_PRDT_ATTR = 0x2,
393 OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
394 OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
395 OCS_PEER_COMM_FAILURE = 0x5,
396 OCS_ABORTED = 0x6,
397 OCS_FATAL_ERROR = 0x7,
398 OCS_DEVICE_FATAL_ERROR = 0x8,
399 OCS_INVALID_CRYPTO_CONFIG = 0x9,
400 OCS_GENERAL_CRYPTO_ERROR = 0xA,
401 OCS_INVALID_COMMAND_STATUS = 0x0F,
402 };
403
404 enum {
405 MASK_OCS = 0x0F,
406 };
407
408 /* The maximum length of the data byte count field in the PRDT is 256KB */
409 #define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024)
410 /* The granularity of the data byte count field in the PRDT is 32-bit */
411 #define PRDT_DATA_BYTE_COUNT_PAD 4
412
413 /**
414 * struct ufshcd_sg_entry - UFSHCI PRD Entry
415 * @addr: Physical address; DW-0 and DW-1.
416 * @reserved: Reserved for future use DW-2
417 * @size: size of physical segment DW-3
418 */
419 struct ufshcd_sg_entry {
420 __le64 addr;
421 __le32 reserved;
422 __le32 size;
423 /*
424 * followed by variant-specific fields if
425 * hba->sg_entry_size != sizeof(struct ufshcd_sg_entry)
426 */
427 };
428
429 /**
430 * struct utp_transfer_cmd_desc - UTP Command Descriptor (UCD)
431 * @command_upiu: Command UPIU Frame address
432 * @response_upiu: Response UPIU Frame address
433 * @prd_table: Physical Region Descriptor: an array of SG_ALL struct
434 * ufshcd_sg_entry's. Variant-specific fields may be present after each.
435 */
436 struct utp_transfer_cmd_desc {
437 u8 command_upiu[ALIGNED_UPIU_SIZE];
438 u8 response_upiu[ALIGNED_UPIU_SIZE];
439 u8 prd_table[];
440 };
441
442 #define sizeof_utp_transfer_cmd_desc(hba) \
443 (sizeof(struct utp_transfer_cmd_desc) + SG_ALL * (hba)->sg_entry_size)
444
445 /**
446 * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
447 * @dword0: Descriptor Header DW0
448 * @dword1: Descriptor Header DW1
449 * @dword2: Descriptor Header DW2
450 * @dword3: Descriptor Header DW3
451 */
452 struct request_desc_header {
453 __le32 dword_0;
454 __le32 dword_1;
455 __le32 dword_2;
456 __le32 dword_3;
457 };
458
459 /**
460 * struct utp_transfer_req_desc - UTP Transfer Request Descriptor (UTRD)
461 * @header: UTRD header DW-0 to DW-3
462 * @command_desc_base_addr_lo: UCD base address low DW-4
463 * @command_desc_base_addr_hi: UCD base address high DW-5
464 * @response_upiu_length: response UPIU length DW-6
465 * @response_upiu_offset: response UPIU offset DW-6
466 * @prd_table_length: Physical region descriptor length DW-7
467 * @prd_table_offset: Physical region descriptor offset DW-7
468 */
469 struct utp_transfer_req_desc {
470
471 /* DW 0-3 */
472 struct request_desc_header header;
473
474 /* DW 4-5*/
475 __le32 command_desc_base_addr_lo;
476 __le32 command_desc_base_addr_hi;
477
478 /* DW 6 */
479 __le16 response_upiu_length;
480 __le16 response_upiu_offset;
481
482 /* DW 7 */
483 __le16 prd_table_length;
484 __le16 prd_table_offset;
485 };
486
487 /*
488 * UTMRD structure.
489 */
490 struct utp_task_req_desc {
491 /* DW 0-3 */
492 struct request_desc_header header;
493
494 /* DW 4-11 - Task request UPIU structure */
495 struct {
496 struct utp_upiu_header req_header;
497 __be32 input_param1;
498 __be32 input_param2;
499 __be32 input_param3;
500 __be32 __reserved1[2];
501 } upiu_req;
502
503 /* DW 12-19 - Task Management Response UPIU structure */
504 struct {
505 struct utp_upiu_header rsp_header;
506 __be32 output_param1;
507 __be32 output_param2;
508 __be32 __reserved2[3];
509 } upiu_rsp;
510 };
511
512 #endif /* End of Header */
513