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Searched refs:REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/msm/adreno/
Da6xx_gmu.xml.h237 #define REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL 0x000050c0 macro
Da6xx_gmu.c624 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400); in a6xx_gmu_power_config()
630 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, in a6xx_gmu_power_config()
637 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, in a6xx_gmu_power_config()