Searched refs:REG_AXXX_CP_RB_WPTR (Results 1 – 3 of 3) sorted by relevance
52 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a2xx_submit()98 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a2xx_me_init()
83 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a3xx_submit()109 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a3xx_me_init()
249 #define REG_AXXX_CP_RB_WPTR 0x000001c5 macro