Searched refs:REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2 (Results 1 – 2 of 2) sorted by relevance
536 pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2, data); in pll_db_commit_14nm()642 div_frac_start |= (pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2) in dsi_pll_14nm_vco_recalc_rate()
1693 #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2 0x000000b8 macro