Searched refs:REG_DSI_14nm_PHY_PLL_VREF_CFG1 (Results 1 – 2 of 2) sorted by relevance
771 pll_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10); in dsi_pll_14nm_enable_seq()
1653 #define REG_DSI_14nm_PHY_PLL_VREF_CFG1 0x0000005c macro