Searched refs:REG_DSI_28nm_PHY_PLL_CAL_CFG1 (Results 1 – 2 of 2) sorted by relevance
405 pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_CAL_CFG1, 0x34, 500); in dsi_pll_28nm_enable_seq_lp()
1234 #define REG_DSI_28nm_PHY_PLL_CAL_CFG1 0x00000070 macro