Searched refs:REG_DSI_28nm_PHY_PLL_CAL_CFG3 (Results 1 – 2 of 2) sorted by relevance
212 pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG3, 0x2b); in dsi_pll_28nm_clk_set_rate()
1238 #define REG_DSI_28nm_PHY_PLL_CAL_CFG3 0x00000078 macro