Searched refs:REG_DSI_28nm_PHY_PLL_CAL_CFG6 (Results 1 – 2 of 2) sorted by relevance
232 pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG6, 0x30); in dsi_pll_28nm_clk_set_rate()
1244 #define REG_DSI_28nm_PHY_PLL_CAL_CFG6 0x00000084 macro