Searched refs:REG_DSI_28nm_PHY_PLL_CAL_CFG8 (Results 1 – 2 of 2) sorted by relevance
234 pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG8, 0x60); in dsi_pll_28nm_clk_set_rate()
1248 #define REG_DSI_28nm_PHY_PLL_CAL_CFG8 0x0000008c macro