Searched refs:REG_DSI_28nm_PHY_PLL_GLB_CFG (Results 1 – 2 of 2) sorted by relevance
| /drivers/gpu/drm/msm/dsi/pll/ |
| D | dsi_pll_28nm.c | 332 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1); in dsi_pll_28nm_enable_seq_hpm()
335 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); in dsi_pll_28nm_enable_seq_hpm()
338 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); in dsi_pll_28nm_enable_seq_hpm()
341 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); in dsi_pll_28nm_enable_seq_hpm()
362 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1); in dsi_pll_28nm_enable_seq_hpm()
365 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); in dsi_pll_28nm_enable_seq_hpm()
368 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 250); in dsi_pll_28nm_enable_seq_hpm()
371 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); in dsi_pll_28nm_enable_seq_hpm()
374 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); in dsi_pll_28nm_enable_seq_hpm()
377 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); in dsi_pll_28nm_enable_seq_hpm()
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| /drivers/gpu/drm/msm/dsi/ |
| D | dsi.xml.h | 1158 #define REG_DSI_28nm_PHY_PLL_GLB_CFG 0x00000020 macro
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