Searched refs:REG_DSI_28nm_PHY_PLL_REFCLK_CFG (Results 1 – 2 of 2) sorted by relevance
227 pll_write(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG, refclk_cfg); in dsi_pll_28nm_clk_set_rate()266 doubler = pll_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) & in dsi_pll_28nm_clk_recalc_rate()
1140 #define REG_DSI_28nm_PHY_PLL_REFCLK_CFG 0x00000000 macro