Searched refs:REG_DSI_28nm_PHY_PLL_SDM_CFG0 (Results 1 – 2 of 2) sorted by relevance
230 pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0, sdm_cfg0); in dsi_pll_28nm_clk_set_rate()271 sdm0 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0); in dsi_pll_28nm_clk_recalc_rate()275 pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0), in dsi_pll_28nm_clk_recalc_rate()
1174 #define REG_DSI_28nm_PHY_PLL_SDM_CFG0 0x00000038 macro