Searched refs:REG_DSI_28nm_PHY_PLL_SDM_CFG2 (Results 1 – 2 of 2) sorted by relevance
217 pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2, in dsi_pll_28nm_clk_set_rate()284 sdm2 = FIELD(pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2), in dsi_pll_28nm_clk_recalc_rate()
1197 #define REG_DSI_28nm_PHY_PLL_SDM_CFG2 0x00000040 macro