Searched refs:REG_DSI_28nm_PHY_PLL_SDM_CFG3 (Results 1 – 2 of 2) sorted by relevance
219 pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3, in dsi_pll_28nm_clk_set_rate()286 sdm3 = FIELD(pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3), in dsi_pll_28nm_clk_recalc_rate()
1205 #define REG_DSI_28nm_PHY_PLL_SDM_CFG3 0x00000044 macro