Searched refs:REG_DSI_7nm_PHY_CMN_CLK_CFG0 (Results 1 – 2 of 2) sorted by relevance
570 cmn_clk_cfg0 = pll_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0); in dsi_pll_7nm_save_state()595 pll_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0, in dsi_pll_7nm_restore_state()739 REG_DSI_7nm_PHY_CMN_CLK_CFG0, in pll_7nm_register()812 REG_DSI_7nm_PHY_CMN_CLK_CFG0, in pll_7nm_register()
1897 #define REG_DSI_7nm_PHY_CMN_CLK_CFG0 0x00000010 macro