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Searched refs:REG_DSI_7nm_PHY_CMN_PLL_CNTRL (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/msm/dsi/phy/
Ddsi_phy_7nm.c16 data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL); in dsi_phy_hw_v4_0_is_pll_on()
130 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0x00); in dsi_7nm_phy_enable()
/drivers/gpu/drm/msm/dsi/pll/
Ddsi_pll_7nm.c445 pll_write(pll_7nm->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0x01); in dsi_pll_7nm_vco_prepare()
496 pll_write(pll_7nm->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0); in dsi_pll_7nm_vco_unprepare()
/drivers/gpu/drm/msm/dsi/
Ddsi.xml.h1919 #define REG_DSI_7nm_PHY_CMN_PLL_CNTRL 0x0000003c macro