Searched refs:REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5 (Results 1 – 2 of 2) sorted by relevance
181 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5, timing->hs_zero); in dsi_7nm_phy_enable()
1943 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5 0x000000c8 macro