Searched refs:REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1 (Results 1 – 2 of 2) sorted by relevance
324 pll_write(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1, reg->decimal_div_start); in dsi_pll_commit()520 dec = pll_read(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1); in dsi_pll_7nm_vco_recalc_rate()
2119 #define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000e0 macro