Searched refs:REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER (Results 1 – 2 of 2) sorted by relevance
292 pll_write(base + REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e); in dsi_pll_config_hzindep_reg()
2025 #define REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000024 macro