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Searched refs:REG_SET_4 (Results 1 – 21 of 21) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dpp_cm.c605 REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0, in dpp20_program_shaper_luta_settings()
612 REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0, in dpp20_program_shaper_luta_settings()
619 REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0, in dpp20_program_shaper_luta_settings()
626 REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0, in dpp20_program_shaper_luta_settings()
633 REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0, in dpp20_program_shaper_luta_settings()
640 REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0, in dpp20_program_shaper_luta_settings()
647 REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0, in dpp20_program_shaper_luta_settings()
654 REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0, in dpp20_program_shaper_luta_settings()
661 REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0, in dpp20_program_shaper_luta_settings()
668 REG_SET_4(CM_SHAPER_RAMA_REGION_18_19, 0, in dpp20_program_shaper_luta_settings()
[all …]
Ddcn20_stream_encoder.c168 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
178 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
188 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
198 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
244 REG_SET_4(AFMT_GENERIC_HDR, 0, in enc2_update_gsp7_128_info_packet()
Ddcn20_dsc.c563 REG_SET_4(DSCC_CONFIG0, 0, in dsc_write_to_registers()
575 REG_SET_4(DSCC_INTERRUPT_CONTROL_STATUS, 0, in dsc_write_to_registers()
644 REG_SET_4(DSCC_PPS_CONFIG12, 0, in dsc_write_to_registers()
650 REG_SET_4(DSCC_PPS_CONFIG13, 0, in dsc_write_to_registers()
656 REG_SET_4(DSCC_PPS_CONFIG14, 0, in dsc_write_to_registers()
Ddcn20_dwb_scl.c706 REG_SET_4(WBSCL_COEF_RAM_TAP_DATA, 0, in wbscl_set_scaler_filter()
Ddcn20_hubp.c203 REG_SET_4(DCN_EXPANSION_MODE, 0, in hubp2_program_requestor()
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dpp.c812 REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0, in dpp3_program_shaper_luta_settings()
819 REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0, in dpp3_program_shaper_luta_settings()
826 REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0, in dpp3_program_shaper_luta_settings()
833 REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0, in dpp3_program_shaper_luta_settings()
840 REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0, in dpp3_program_shaper_luta_settings()
847 REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0, in dpp3_program_shaper_luta_settings()
854 REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0, in dpp3_program_shaper_luta_settings()
861 REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0, in dpp3_program_shaper_luta_settings()
868 REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0, in dpp3_program_shaper_luta_settings()
875 REG_SET_4(CM_SHAPER_RAMA_REGION_18_19, 0, in dpp3_program_shaper_luta_settings()
[all …]
Ddcn30_mpc.c492 REG_SET_4(SHAPER_RAMA_REGION_0_1[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
499 REG_SET_4(SHAPER_RAMA_REGION_2_3[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
506 REG_SET_4(SHAPER_RAMA_REGION_4_5[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
513 REG_SET_4(SHAPER_RAMA_REGION_6_7[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
520 REG_SET_4(SHAPER_RAMA_REGION_8_9[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
527 REG_SET_4(SHAPER_RAMA_REGION_10_11[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
534 REG_SET_4(SHAPER_RAMA_REGION_12_13[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
541 REG_SET_4(SHAPER_RAMA_REGION_14_15[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
549 REG_SET_4(SHAPER_RAMA_REGION_16_17[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
556 REG_SET_4(SHAPER_RAMA_REGION_18_19[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
[all …]
Ddcn30_dio_stream_encoder.c238 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
248 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
258 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
268 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
278 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
288 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
298 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
Ddcn30_vpg.c87 REG_SET_4(VPG_GENERIC_PACKET_DATA, 0, in vpg3_update_generic_info_packet()
Ddcn30_cm_common.c92 REG_SET_4(reg_region_cur, 0, in cm_helper_program_gamcor_xfer_func()
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_transform.c249 REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0, in program_multi_taps_filter()
1515 REG_SET_4(REGAMMA_CNTLA_REGION_0_1, 0, in regamma_config_regions_and_segments()
1522 REG_SET_4(REGAMMA_CNTLA_REGION_2_3, 0, in regamma_config_regions_and_segments()
1529 REG_SET_4(REGAMMA_CNTLA_REGION_4_5, 0, in regamma_config_regions_and_segments()
1536 REG_SET_4(REGAMMA_CNTLA_REGION_6_7, 0, in regamma_config_regions_and_segments()
1543 REG_SET_4(REGAMMA_CNTLA_REGION_8_9, 0, in regamma_config_regions_and_segments()
1550 REG_SET_4(REGAMMA_CNTLA_REGION_10_11, 0, in regamma_config_regions_and_segments()
1557 REG_SET_4(REGAMMA_CNTLA_REGION_12_13, 0, in regamma_config_regions_and_segments()
1564 REG_SET_4(REGAMMA_CNTLA_REGION_14_15, 0, in regamma_config_regions_and_segments()
Ddce_stream_encoder.c110 REG_SET_4(AFMT_GENERIC_HDR, 0, in dce110_update_generic_info_packet()
501 REG_SET_4(DP_MSA_TIMING_PARAM3, 0, in dce110_stream_encoder_dp_set_stream_attribute()
Ddce_i2c_hw.c227 value = REG_SET_4(DC_I2C_DATA, 0, in process_transaction()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_dpp_dscl.c282 REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0, in dpp1_dscl_set_scaler_filter()
570 REG_SET_4(SCL_TAP_CONTROL, 0, in dpp1_dscl_set_scaler_auto_scale()
730 REG_SET_4(SCL_TAP_CONTROL, 0, in dpp1_dscl_set_scaler_manual_scale()
Ddcn10_stream_encoder.c97 REG_SET_4(AFMT_GENERIC_HDR, 0, in enc1_update_generic_info_packet()
456 REG_SET_4(DP_MSA_TIMING_PARAM3, 0, in enc1_stream_encoder_dp_set_stream_attribute()
797 REG_SET_4(AFMT_GENERIC_HDR, 0, in enc1_stream_encoder_send_immediate_sdp_message()
Ddcn10_optc.c776 REG_SET_4(OTG_TRIGA_CNTL, 0, in optc1_enable_crtc_reset()
1189 REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0, in optc1_set_test_pattern()
Ddcn10_cm_common.c115 REG_SET_4(reg_region_cur, 0, in cm_helper_program_xfer_func()
Ddcn10_hubp.c560 REG_SET_4(DCN_EXPANSION_MODE, 0, in hubp1_program_requestor()
/drivers/gpu/drm/amd/display/dmub/src/
Ddmub_reg.h76 #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \ macro
/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_hubp.c145 REG_SET_4(DCN_EXPANSION_MODE, 0, in hubp21_program_requestor()
/drivers/gpu/drm/amd/display/dc/inc/
Dreg_helper.h78 #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \ macro