Searched refs:REG_UPDATE_SEQ_2 (Results 1 – 3 of 3) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_aux.c | 192 REG_UPDATE_SEQ_2(AUXN_IMPCAL, in submit_channel_request()
196 REG_UPDATE_SEQ_2(AUXP_IMPCAL, in submit_channel_request()
201 REG_UPDATE_SEQ_2(AUXN_IMPCAL, in submit_channel_request()
207 REG_UPDATE_SEQ_2(AUXP_IMPCAL, in submit_channel_request()
495 …REG_UPDATE_SEQ_2(AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, length, AUX_RX_TIMEOUT_LEN_MUL, multipl… in dce_aux_configure_timeout()
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hubbub.c | 240 REG_UPDATE_SEQ_2(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, in hubbub1_wm_change_req_wa()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | reg_helper.h | 382 #define REG_UPDATE_SEQ_2(reg, f1, v1, f2, v2) \ macro
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