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Searched refs:RLC_SERDES_WR_CTRL__BPM_ADDR_MASK (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dgfx_v7_0.c3596 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | in gfx_v7_0_enable_cgcg()
3650 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | in gfx_v7_0_enable_mgcg()
3701 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK; in gfx_v7_0_enable_mgcg()
/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h7268 #define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0x000000ffL macro
Dgfx_7_2_sh_mask.h8019 #define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0xff macro
Dgfx_8_0_sh_mask.h8939 #define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0xff macro
Dgfx_8_1_sh_mask.h9481 #define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0xff macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h23278 #define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK … macro
Dgc_9_1_sh_mask.h24569 #define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK … macro
Dgc_9_2_1_sh_mask.h24633 #define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK … macro