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1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4  */
5 #ifndef ATH11K_RX_DESC_H
6 #define ATH11K_RX_DESC_H
7 
8 enum rx_desc_rxpcu_filter {
9 	RX_DESC_RXPCU_FILTER_PASS,
10 	RX_DESC_RXPCU_FILTER_MONITOR_CLIENT,
11 	RX_DESC_RXPCU_FILTER_MONITOR_OTHER,
12 };
13 
14 /* rxpcu_filter_pass
15  *		This MPDU passed the normal frame filter programming of rxpcu.
16  *
17  * rxpcu_filter_monitor_client
18  *		 This MPDU did not pass the regular frame filter and would
19  *		 have been dropped, were it not for the frame fitting into the
20  *		 'monitor_client' category.
21  *
22  * rxpcu_filter_monitor_other
23  *		This MPDU did not pass the regular frame filter and also did
24  *		not pass the rxpcu_monitor_client filter. It would have been
25  *		dropped accept that it did pass the 'monitor_other' category.
26  */
27 
28 #define RX_DESC_INFO0_RXPCU_MPDU_FITLER	GENMASK(1, 0)
29 #define RX_DESC_INFO0_SW_FRAME_GRP_ID	GENMASK(8, 2)
30 
31 enum rx_desc_sw_frame_grp_id {
32 	RX_DESC_SW_FRAME_GRP_ID_NDP_FRAME,
33 	RX_DESC_SW_FRAME_GRP_ID_MCAST_DATA,
34 	RX_DESC_SW_FRAME_GRP_ID_UCAST_DATA,
35 	RX_DESC_SW_FRAME_GRP_ID_NULL_DATA,
36 	RX_DESC_SW_FRAME_GRP_ID_MGMT_0000,
37 	RX_DESC_SW_FRAME_GRP_ID_MGMT_0001,
38 	RX_DESC_SW_FRAME_GRP_ID_MGMT_0010,
39 	RX_DESC_SW_FRAME_GRP_ID_MGMT_0011,
40 	RX_DESC_SW_FRAME_GRP_ID_MGMT_0100,
41 	RX_DESC_SW_FRAME_GRP_ID_MGMT_0101,
42 	RX_DESC_SW_FRAME_GRP_ID_MGMT_0110,
43 	RX_DESC_SW_FRAME_GRP_ID_MGMT_0111,
44 	RX_DESC_SW_FRAME_GRP_ID_MGMT_1000,
45 	RX_DESC_SW_FRAME_GRP_ID_MGMT_1001,
46 	RX_DESC_SW_FRAME_GRP_ID_MGMT_1010,
47 	RX_DESC_SW_FRAME_GRP_ID_MGMT_1011,
48 	RX_DESC_SW_FRAME_GRP_ID_MGMT_1100,
49 	RX_DESC_SW_FRAME_GRP_ID_MGMT_1101,
50 	RX_DESC_SW_FRAME_GRP_ID_MGMT_1110,
51 	RX_DESC_SW_FRAME_GRP_ID_MGMT_1111,
52 	RX_DESC_SW_FRAME_GRP_ID_CTRL_0000,
53 	RX_DESC_SW_FRAME_GRP_ID_CTRL_0001,
54 	RX_DESC_SW_FRAME_GRP_ID_CTRL_0010,
55 	RX_DESC_SW_FRAME_GRP_ID_CTRL_0011,
56 	RX_DESC_SW_FRAME_GRP_ID_CTRL_0100,
57 	RX_DESC_SW_FRAME_GRP_ID_CTRL_0101,
58 	RX_DESC_SW_FRAME_GRP_ID_CTRL_0110,
59 	RX_DESC_SW_FRAME_GRP_ID_CTRL_0111,
60 	RX_DESC_SW_FRAME_GRP_ID_CTRL_1000,
61 	RX_DESC_SW_FRAME_GRP_ID_CTRL_1001,
62 	RX_DESC_SW_FRAME_GRP_ID_CTRL_1010,
63 	RX_DESC_SW_FRAME_GRP_ID_CTRL_1011,
64 	RX_DESC_SW_FRAME_GRP_ID_CTRL_1100,
65 	RX_DESC_SW_FRAME_GRP_ID_CTRL_1101,
66 	RX_DESC_SW_FRAME_GRP_ID_CTRL_1110,
67 	RX_DESC_SW_FRAME_GRP_ID_CTRL_1111,
68 	RX_DESC_SW_FRAME_GRP_ID_UNSUPPORTED,
69 	RX_DESC_SW_FRAME_GRP_ID_PHY_ERR,
70 };
71 
72 enum rx_desc_decap_type {
73 	RX_DESC_DECAP_TYPE_RAW,
74 	RX_DESC_DECAP_TYPE_NATIVE_WIFI,
75 	RX_DESC_DECAP_TYPE_ETHERNET2_DIX,
76 	RX_DESC_DECAP_TYPE_8023,
77 };
78 
79 enum rx_desc_decrypt_status_code {
80 	RX_DESC_DECRYPT_STATUS_CODE_OK,
81 	RX_DESC_DECRYPT_STATUS_CODE_UNPROTECTED_FRAME,
82 	RX_DESC_DECRYPT_STATUS_CODE_DATA_ERR,
83 	RX_DESC_DECRYPT_STATUS_CODE_KEY_INVALID,
84 	RX_DESC_DECRYPT_STATUS_CODE_PEER_ENTRY_INVALID,
85 	RX_DESC_DECRYPT_STATUS_CODE_OTHER,
86 };
87 
88 #define RX_ATTENTION_INFO1_FIRST_MPDU		BIT(0)
89 #define RX_ATTENTION_INFO1_RSVD_1A		BIT(1)
90 #define RX_ATTENTION_INFO1_MCAST_BCAST		BIT(2)
91 #define RX_ATTENTION_INFO1_AST_IDX_NOT_FOUND	BIT(3)
92 #define RX_ATTENTION_INFO1_AST_IDX_TIMEDOUT	BIT(4)
93 #define RX_ATTENTION_INFO1_POWER_MGMT		BIT(5)
94 #define RX_ATTENTION_INFO1_NON_QOS		BIT(6)
95 #define RX_ATTENTION_INFO1_NULL_DATA		BIT(7)
96 #define RX_ATTENTION_INFO1_MGMT_TYPE		BIT(8)
97 #define RX_ATTENTION_INFO1_CTRL_TYPE		BIT(9)
98 #define RX_ATTENTION_INFO1_MORE_DATA		BIT(10)
99 #define RX_ATTENTION_INFO1_EOSP			BIT(11)
100 #define RX_ATTENTION_INFO1_A_MSDU_ERROR		BIT(12)
101 #define RX_ATTENTION_INFO1_FRAGMENT		BIT(13)
102 #define RX_ATTENTION_INFO1_ORDER		BIT(14)
103 #define RX_ATTENTION_INFO1_CCE_MATCH		BIT(15)
104 #define RX_ATTENTION_INFO1_OVERFLOW_ERR		BIT(16)
105 #define RX_ATTENTION_INFO1_MSDU_LEN_ERR		BIT(17)
106 #define RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL	BIT(18)
107 #define RX_ATTENTION_INFO1_IP_CKSUM_FAIL	BIT(19)
108 #define RX_ATTENTION_INFO1_SA_IDX_INVALID	BIT(20)
109 #define RX_ATTENTION_INFO1_DA_IDX_INVALID	BIT(21)
110 #define RX_ATTENTION_INFO1_RSVD_1B		BIT(22)
111 #define RX_ATTENTION_INFO1_RX_IN_TX_DECRYPT_BYP	BIT(23)
112 #define RX_ATTENTION_INFO1_ENCRYPT_REQUIRED	BIT(24)
113 #define RX_ATTENTION_INFO1_DIRECTED		BIT(25)
114 #define RX_ATTENTION_INFO1_BUFFER_FRAGMENT	BIT(26)
115 #define RX_ATTENTION_INFO1_MPDU_LEN_ERR		BIT(27)
116 #define RX_ATTENTION_INFO1_TKIP_MIC_ERR		BIT(28)
117 #define RX_ATTENTION_INFO1_DECRYPT_ERR		BIT(29)
118 #define RX_ATTENTION_INFO1_UNDECRYPT_FRAME_ERR	BIT(30)
119 #define RX_ATTENTION_INFO1_FCS_ERR		BIT(31)
120 
121 #define RX_ATTENTION_INFO2_FLOW_IDX_TIMEOUT	BIT(0)
122 #define RX_ATTENTION_INFO2_FLOW_IDX_INVALID	BIT(1)
123 #define RX_ATTENTION_INFO2_WIFI_PARSER_ERR	BIT(2)
124 #define RX_ATTENTION_INFO2_AMSDU_PARSER_ERR	BIT(3)
125 #define RX_ATTENTION_INFO2_SA_IDX_TIMEOUT	BIT(4)
126 #define RX_ATTENTION_INFO2_DA_IDX_TIMEOUT	BIT(5)
127 #define RX_ATTENTION_INFO2_MSDU_LIMIT_ERR	BIT(6)
128 #define RX_ATTENTION_INFO2_DA_IS_VALID		BIT(7)
129 #define RX_ATTENTION_INFO2_DA_IS_MCBC		BIT(8)
130 #define RX_ATTENTION_INFO2_SA_IS_VALID		BIT(9)
131 #define RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE	GENMASK(12, 10)
132 #define RX_ATTENTION_INFO2_RX_BITMAP_NOT_UPDED	BIT(13)
133 #define RX_ATTENTION_INFO2_MSDU_DONE		BIT(31)
134 
135 struct rx_attention {
136 	__le16 info0;
137 	__le16 phy_ppdu_id;
138 	__le32 info1;
139 	__le32 info2;
140 } __packed;
141 
142 /* rx_attention
143  *
144  * rxpcu_mpdu_filter_in_category
145  *		Field indicates what the reason was that this mpdu frame
146  *		was allowed to come into the receive path by rxpcu. Values
147  *		are defined in enum %RX_DESC_RXPCU_FILTER_*.
148  *
149  * sw_frame_group_id
150  *		SW processes frames based on certain classifications. Values
151  *		are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*.
152  *
153  * phy_ppdu_id
154  *		A ppdu counter value that PHY increments for every PPDU
155  *		received. The counter value wraps around.
156  *
157  * first_mpdu
158  *		Indicates the first MSDU of the PPDU.  If both first_mpdu
159  *		and last_mpdu are set in the MSDU then this is a not an
160  *		A-MPDU frame but a stand alone MPDU.  Interior MPDU in an
161  *		A-MPDU shall have both first_mpdu and last_mpdu bits set to
162  *		0.  The PPDU start status will only be valid when this bit
163  *		is set.
164  *
165  * mcast_bcast
166  *		Multicast / broadcast indicator.  Only set when the MAC
167  *		address 1 bit 0 is set indicating mcast/bcast and the BSSID
168  *		matches one of the 4 BSSID registers. Only set when
169  *		first_msdu is set.
170  *
171  * ast_index_not_found
172  *		Only valid when first_msdu is set. Indicates no AST matching
173  *		entries within the the max search count.
174  *
175  * ast_index_timeout
176  *		Only valid when first_msdu is set. Indicates an unsuccessful
177  *		search in the address search table due to timeout.
178  *
179  * power_mgmt
180  *		Power management bit set in the 802.11 header.  Only set
181  *		when first_msdu is set.
182  *
183  * non_qos
184  *		Set if packet is not a non-QoS data frame.  Only set when
185  *		first_msdu is set.
186  *
187  * null_data
188  *		Set if frame type indicates either null data or QoS null
189  *		data format.  Only set when first_msdu is set.
190  *
191  * mgmt_type
192  *		Set if packet is a management packet.  Only set when
193  *		first_msdu is set.
194  *
195  * ctrl_type
196  *		Set if packet is a control packet.  Only set when first_msdu
197  *		is set.
198  *
199  * more_data
200  *		Set if more bit in frame control is set.  Only set when
201  *		first_msdu is set.
202  *
203  * eosp
204  *		Set if the EOSP (end of service period) bit in the QoS
205  *		control field is set.  Only set when first_msdu is set.
206  *
207  * a_msdu_error
208  *		Set if number of MSDUs in A-MSDU is above a threshold or if the
209  *		size of the MSDU is invalid. This receive buffer will contain
210  *		all of the remainder of MSDUs in this MPDU w/o decapsulation.
211  *
212  * fragment
213  *		Indicates that this is an 802.11 fragment frame.  This is
214  *		set when either the more_frag bit is set in the frame
215  *		control or the fragment number is not zero.  Only set when
216  *		first_msdu is set.
217  *
218  * order
219  *		Set if the order bit in the frame control is set.  Only set
220  *		when first_msdu is set.
221  *
222  * cce_match
223  *		Indicates that this status has a corresponding MSDU that
224  *		requires FW processing. The OLE will have classification
225  *		ring mask registers which will indicate the ring(s) for
226  *		packets and descriptors which need FW attention.
227  *
228  * overflow_err
229  *		PCU Receive FIFO does not have enough space to store the
230  *		full receive packet.  Enough space is reserved in the
231  *		receive FIFO for the status is written.  This MPDU remaining
232  *		packets in the PPDU will be filtered and no Ack response
233  *		will be transmitted.
234  *
235  * msdu_length_err
236  *		Indicates that the MSDU length from the 802.3 encapsulated
237  *		length field extends beyond the MPDU boundary.
238  *
239  * tcp_udp_chksum_fail
240  *		Indicates that the computed checksum (tcp_udp_chksum) did
241  *		not match the checksum in the TCP/UDP header.
242  *
243  * ip_chksum_fail
244  *		Indicates that the computed checksum did not match the
245  *		checksum in the IP header.
246  *
247  * sa_idx_invalid
248  *		Indicates no matching entry was found in the address search
249  *		table for the source MAC address.
250  *
251  * da_idx_invalid
252  *		Indicates no matching entry was found in the address search
253  *		table for the destination MAC address.
254  *
255  * rx_in_tx_decrypt_byp
256  *		Indicates that RX packet is not decrypted as Crypto is busy
257  *		with TX packet processing.
258  *
259  * encrypt_required
260  *		Indicates that this data type frame is not encrypted even if
261  *		the policy for this MPDU requires encryption as indicated in
262  *		the peer table key type.
263  *
264  * directed
265  *		MPDU is a directed packet which means that the RA matched
266  *		our STA addresses.  In proxySTA it means that the TA matched
267  *		an entry in our address search table with the corresponding
268  *		'no_ack' bit is the address search entry cleared.
269  *
270  * buffer_fragment
271  *		Indicates that at least one of the rx buffers has been
272  *		fragmented.  If set the FW should look at the rx_frag_info
273  *		descriptor described below.
274  *
275  * mpdu_length_err
276  *		Indicates that the MPDU was pre-maturely terminated
277  *		resulting in a truncated MPDU.  Don't trust the MPDU length
278  *		field.
279  *
280  * tkip_mic_err
281  *		Indicates that the MPDU Michael integrity check failed
282  *
283  * decrypt_err
284  *		Indicates that the MPDU decrypt integrity check failed
285  *
286  * fcs_err
287  *		Indicates that the MPDU FCS check failed
288  *
289  * flow_idx_timeout
290  *		Indicates an unsuccessful flow search due to the expiring of
291  *		the search timer.
292  *
293  * flow_idx_invalid
294  *		flow id is not valid.
295  *
296  * amsdu_parser_error
297  *		A-MSDU could not be properly de-agregated.
298  *
299  * sa_idx_timeout
300  *		Indicates an unsuccessful search for the source MAC address
301  *		due to the expiring of the search timer.
302  *
303  * da_idx_timeout
304  *		Indicates an unsuccessful search for the destination MAC
305  *		address due to the expiring of the search timer.
306  *
307  * msdu_limit_error
308  *		Indicates that the MSDU threshold was exceeded and thus
309  *		all the rest of the MSDUs will not be scattered and will not
310  *		be decasulated but will be DMA'ed in RAW format as a single
311  *		MSDU buffer.
312  *
313  * da_is_valid
314  *		Indicates that OLE found a valid DA entry.
315  *
316  * da_is_mcbc
317  *		Field Only valid if da_is_valid is set. Indicates the DA address
318  *		was a Multicast or Broadcast address.
319  *
320  * sa_is_valid
321  *		Indicates that OLE found a valid SA entry.
322  *
323  * decrypt_status_code
324  *		Field provides insight into the decryption performed. Values are
325  *		defined in enum %RX_DESC_DECRYPT_STATUS_CODE*.
326  *
327  * rx_bitmap_not_updated
328  *		Frame is received, but RXPCU could not update the receive bitmap
329  *		due to (temporary) fifo constraints.
330  *
331  * msdu_done
332  *		If set indicates that the RX packet data, RX header data, RX
333  *		PPDU start descriptor, RX MPDU start/end descriptor, RX MSDU
334  *		start/end descriptors and RX Attention descriptor are all
335  *		valid.  This bit must be in the last octet of the
336  *		descriptor.
337  */
338 
339 #define RX_MPDU_START_INFO0_NDP_FRAME		BIT(9)
340 #define RX_MPDU_START_INFO0_PHY_ERR		BIT(10)
341 #define RX_MPDU_START_INFO0_PHY_ERR_MPDU_HDR	BIT(11)
342 #define RX_MPDU_START_INFO0_PROTO_VER_ERR	BIT(12)
343 #define RX_MPDU_START_INFO0_AST_LOOKUP_VALID	BIT(13)
344 
345 #define RX_MPDU_START_INFO1_MPDU_FCTRL_VALID	BIT(0)
346 #define RX_MPDU_START_INFO1_MPDU_DUR_VALID	BIT(1)
347 #define RX_MPDU_START_INFO1_MAC_ADDR1_VALID	BIT(2)
348 #define RX_MPDU_START_INFO1_MAC_ADDR2_VALID	BIT(3)
349 #define RX_MPDU_START_INFO1_MAC_ADDR3_VALID	BIT(4)
350 #define RX_MPDU_START_INFO1_MAC_ADDR4_VALID	BIT(5)
351 #define RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID	BIT(6)
352 #define RX_MPDU_START_INFO1_MPDU_QOS_CTRL_VALID	BIT(7)
353 #define RX_MPDU_START_INFO1_MPDU_HT_CTRL_VALID	BIT(8)
354 #define RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID	BIT(9)
355 #define RX_MPDU_START_INFO1_MPDU_FRAG_NUMBER	GENMASK(13, 10)
356 #define RX_MPDU_START_INFO1_MORE_FRAG_FLAG	BIT(14)
357 #define RX_MPDU_START_INFO1_FROM_DS		BIT(16)
358 #define RX_MPDU_START_INFO1_TO_DS		BIT(17)
359 #define RX_MPDU_START_INFO1_ENCRYPTED		BIT(18)
360 #define RX_MPDU_START_INFO1_MPDU_RETRY		BIT(19)
361 #define RX_MPDU_START_INFO1_MPDU_SEQ_NUM	GENMASK(31, 20)
362 
363 #define RX_MPDU_START_INFO2_EPD_EN		BIT(0)
364 #define RX_MPDU_START_INFO2_ALL_FRAME_ENCPD	BIT(1)
365 #define RX_MPDU_START_INFO2_ENC_TYPE		GENMASK(5, 2)
366 #define RX_MPDU_START_INFO2_VAR_WEP_KEY_WIDTH	GENMASK(7, 6)
367 #define RX_MPDU_START_INFO2_MESH_STA		BIT(8)
368 #define RX_MPDU_START_INFO2_BSSID_HIT		BIT(9)
369 #define RX_MPDU_START_INFO2_BSSID_NUM		GENMASK(13, 10)
370 #define RX_MPDU_START_INFO2_TID			GENMASK(17, 14)
371 
372 #define RX_MPDU_START_INFO3_REO_DEST_IND		GENMASK(4, 0)
373 #define RX_MPDU_START_INFO3_FLOW_ID_TOEPLITZ		BIT(7)
374 #define RX_MPDU_START_INFO3_PKT_SEL_FP_UCAST_DATA	BIT(8)
375 #define RX_MPDU_START_INFO3_PKT_SEL_FP_MCAST_DATA	BIT(9)
376 #define RX_MPDU_START_INFO3_PKT_SEL_FP_CTRL_BAR		BIT(10)
377 #define RX_MPDU_START_INFO3_RXDMA0_SRC_RING_SEL		GENMASK(12, 11)
378 #define RX_MPDU_START_INFO3_RXDMA0_DST_RING_SEL		GENMASK(14, 13)
379 
380 #define RX_MPDU_START_INFO4_REO_QUEUE_DESC_HI	GENMASK(7, 0)
381 #define RX_MPDU_START_INFO4_RECV_QUEUE_NUM	GENMASK(23, 8)
382 #define RX_MPDU_START_INFO4_PRE_DELIM_ERR_WARN	BIT(24)
383 #define RX_MPDU_START_INFO4_FIRST_DELIM_ERR	BIT(25)
384 
385 #define RX_MPDU_START_INFO5_KEY_ID		GENMASK(7, 0)
386 #define RX_MPDU_START_INFO5_NEW_PEER_ENTRY	BIT(8)
387 #define RX_MPDU_START_INFO5_DECRYPT_NEEDED	BIT(9)
388 #define RX_MPDU_START_INFO5_DECAP_TYPE		GENMASK(11, 10)
389 #define RX_MPDU_START_INFO5_VLAN_TAG_C_PADDING	BIT(12)
390 #define RX_MPDU_START_INFO5_VLAN_TAG_S_PADDING	BIT(13)
391 #define RX_MPDU_START_INFO5_STRIP_VLAN_TAG_C	BIT(14)
392 #define RX_MPDU_START_INFO5_STRIP_VLAN_TAG_S	BIT(15)
393 #define RX_MPDU_START_INFO5_PRE_DELIM_COUNT	GENMASK(27, 16)
394 #define RX_MPDU_START_INFO5_AMPDU_FLAG		BIT(28)
395 #define RX_MPDU_START_INFO5_BAR_FRAME		BIT(29)
396 
397 #define RX_MPDU_START_INFO6_MPDU_LEN		GENMASK(13, 0)
398 #define RX_MPDU_START_INFO6_FIRST_MPDU		BIT(14)
399 #define RX_MPDU_START_INFO6_MCAST_BCAST		BIT(15)
400 #define RX_MPDU_START_INFO6_AST_IDX_NOT_FOUND	BIT(16)
401 #define RX_MPDU_START_INFO6_AST_IDX_TIMEOUT	BIT(17)
402 #define RX_MPDU_START_INFO6_POWER_MGMT		BIT(18)
403 #define RX_MPDU_START_INFO6_NON_QOS		BIT(19)
404 #define RX_MPDU_START_INFO6_NULL_DATA		BIT(20)
405 #define RX_MPDU_START_INFO6_MGMT_TYPE		BIT(21)
406 #define RX_MPDU_START_INFO6_CTRL_TYPE		BIT(22)
407 #define RX_MPDU_START_INFO6_MORE_DATA		BIT(23)
408 #define RX_MPDU_START_INFO6_EOSP		BIT(24)
409 #define RX_MPDU_START_INFO6_FRAGMENT		BIT(25)
410 #define RX_MPDU_START_INFO6_ORDER		BIT(26)
411 #define RX_MPDU_START_INFO6_UAPSD_TRIGGER	BIT(27)
412 #define RX_MPDU_START_INFO6_ENCRYPT_REQUIRED	BIT(28)
413 #define RX_MPDU_START_INFO6_DIRECTED		BIT(29)
414 
415 #define RX_MPDU_START_RAW_MPDU			BIT(0)
416 
417 struct rx_mpdu_start {
418 	__le16 info0;
419 	__le16 phy_ppdu_id;
420 	__le16 ast_index;
421 	__le16 sw_peer_id;
422 	__le32 info1;
423 	__le32 info2;
424 	__le32 pn[4];
425 	__le32 peer_meta_data;
426 	__le32 info3;
427 	__le32 reo_queue_desc_lo;
428 	__le32 info4;
429 	__le32 info5;
430 	__le32 info6;
431 	__le16 frame_ctrl;
432 	__le16 duration;
433 	u8 addr1[ETH_ALEN];
434 	u8 addr2[ETH_ALEN];
435 	u8 addr3[ETH_ALEN];
436 	__le16 seq_ctrl;
437 	u8 addr4[ETH_ALEN];
438 	__le16 qos_ctrl;
439 	__le32 ht_ctrl;
440 	__le32 raw;
441 } __packed;
442 
443 /* rx_mpdu_start
444  *
445  * rxpcu_mpdu_filter_in_category
446  *		Field indicates what the reason was that this mpdu frame
447  *		was allowed to come into the receive path by rxpcu. Values
448  *		are defined in enum %RX_DESC_RXPCU_FILTER_*.
449  *		Note: for ndp frame, if it was expected because the preceding
450  *		NDPA was filter_pass, the setting rxpcu_filter_pass will be
451  *		used. This setting will also be used for every ndp frame in
452  *		case Promiscuous mode is enabled.
453  *
454  * sw_frame_group_id
455  *		SW processes frames based on certain classifications. Values
456  *		are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*.
457  *
458  * ndp_frame
459  *		Indicates that the received frame was an NDP frame.
460  *
461  * phy_err
462  *		Indicates that PHY error was received before MAC received data.
463  *
464  * phy_err_during_mpdu_header
465  *		PHY error was received before MAC received the complete MPDU
466  *		header which was needed for proper decoding.
467  *
468  * protocol_version_err
469  *		RXPCU detected a version error in the frame control field.
470  *
471  * ast_based_lookup_valid
472  *		AST based lookup for this frame has found a valid result.
473  *
474  * phy_ppdu_id
475  *		A ppdu counter value that PHY increments for every PPDU
476  *		received. The counter value wraps around.
477  *
478  * ast_index
479  *		This field indicates the index of the AST entry corresponding
480  *		to this MPDU. It is provided by the GSE module instantiated in
481  *		RXPCU. A value of 0xFFFF indicates an invalid AST index.
482  *
483  * sw_peer_id
484  *		This field indicates a unique peer identifier. It is set equal
485  *		to field 'sw_peer_id' from the AST entry.
486  *
487  * mpdu_frame_control_valid, mpdu_duration_valid, mpdu_qos_control_valid,
488  * mpdu_ht_control_valid, frame_encryption_info_valid
489  *		Indicates that each fields have valid entries.
490  *
491  * mac_addr_adx_valid
492  *		Corresponding mac_addr_adx_{lo/hi} has valid entries.
493  *
494  * from_ds, to_ds
495  *		Valid only when mpdu_frame_control_valid is set. Indicates that
496  *		frame is received from DS and sent to DS.
497  *
498  * encrypted
499  *		Protected bit from the frame control.
500  *
501  * mpdu_retry
502  *		Retry bit from frame control. Only valid when first_msdu is set.
503  *
504  * mpdu_sequence_number
505  *		The sequence number from the 802.11 header.
506  *
507  * epd_en
508  *		If set, use EPD instead of LPD.
509  *
510  * all_frames_shall_be_encrypted
511  *		If set, all frames (data only?) shall be encrypted. If not,
512  *		RX CRYPTO shall set an error flag.
513  *
514  * encrypt_type
515  *		Values are defined in enum %HAL_ENCRYPT_TYPE_.
516  *
517  * mesh_sta
518  *		Indicates a Mesh (11s) STA.
519  *
520  * bssid_hit
521  *		 BSSID of the incoming frame matched one of the 8 BSSID
522  *		 register values.
523  *
524  * bssid_number
525  *		This number indicates which one out of the 8 BSSID register
526  *		values matched the incoming frame.
527  *
528  * tid
529  *		TID field in the QoS control field
530  *
531  * pn
532  *		The PN number.
533  *
534  * peer_meta_data
535  *		Meta data that SW has programmed in the Peer table entry
536  *		of the transmitting STA.
537  *
538  * rx_reo_queue_desc_addr_lo
539  *		Address (lower 32 bits) of the REO queue descriptor.
540  *
541  * rx_reo_queue_desc_addr_hi
542  *		Address (upper 8 bits) of the REO queue descriptor.
543  *
544  * receive_queue_number
545  *		Indicates the MPDU queue ID to which this MPDU link
546  *		descriptor belongs.
547  *
548  * pre_delim_err_warning
549  *		Indicates that a delimiter FCS error was found in between the
550  *		previous MPDU and this MPDU. Note that this is just a warning,
551  *		and does not mean that this MPDU is corrupted in any way. If
552  *		it is, there will be other errors indicated such as FCS or
553  *		decrypt errors.
554  *
555  * first_delim_err
556  *		Indicates that the first delimiter had a FCS failure.
557  *
558  * key_id
559  *		The key ID octet from the IV.
560  *
561  * new_peer_entry
562  *		Set if new RX_PEER_ENTRY TLV follows. If clear, RX_PEER_ENTRY
563  *		doesn't follow so RX DECRYPTION module either uses old peer
564  *		entry or not decrypt.
565  *
566  * decrypt_needed
567  *		When RXPCU sets bit 'ast_index_not_found or ast_index_timeout',
568  *		RXPCU will also ensure that this bit is NOT set. CRYPTO for that
569  *		reason only needs to evaluate this bit and non of the other ones
570  *
571  * decap_type
572  *		Used by the OLE during decapsulation. Values are defined in
573  *		enum %MPDU_START_DECAP_TYPE_*.
574  *
575  * rx_insert_vlan_c_tag_padding
576  * rx_insert_vlan_s_tag_padding
577  *		Insert 4 byte of all zeros as VLAN tag or double VLAN tag if
578  *		the rx payload does not have VLAN.
579  *
580  * strip_vlan_c_tag_decap
581  * strip_vlan_s_tag_decap
582  *		Strip VLAN or double VLAN during decapsulation.
583  *
584  * pre_delim_count
585  *		The number of delimiters before this MPDU. Note that this
586  *		number is cleared at PPDU start. If this MPDU is the first
587  *		received MPDU in the PPDU and this MPDU gets filtered-in,
588  *		this field will indicate the number of delimiters located
589  *		after the last MPDU in the previous PPDU.
590  *
591  *		If this MPDU is located after the first received MPDU in
592  *		an PPDU, this field will indicate the number of delimiters
593  *		located between the previous MPDU and this MPDU.
594  *
595  * ampdu_flag
596  *		Received frame was part of an A-MPDU.
597  *
598  * bar_frame
599  *		Received frame is a BAR frame
600  *
601  * mpdu_length
602  *		MPDU length before decapsulation.
603  *
604  * first_mpdu..directed
605  *		See definition in RX attention descriptor
606  *
607  */
608 
609 enum rx_msdu_start_pkt_type {
610 	RX_MSDU_START_PKT_TYPE_11A,
611 	RX_MSDU_START_PKT_TYPE_11B,
612 	RX_MSDU_START_PKT_TYPE_11N,
613 	RX_MSDU_START_PKT_TYPE_11AC,
614 	RX_MSDU_START_PKT_TYPE_11AX,
615 };
616 
617 enum rx_msdu_start_sgi {
618 	RX_MSDU_START_SGI_0_8_US,
619 	RX_MSDU_START_SGI_0_4_US,
620 	RX_MSDU_START_SGI_1_6_US,
621 	RX_MSDU_START_SGI_3_2_US,
622 };
623 
624 enum rx_msdu_start_recv_bw {
625 	RX_MSDU_START_RECV_BW_20MHZ,
626 	RX_MSDU_START_RECV_BW_40MHZ,
627 	RX_MSDU_START_RECV_BW_80MHZ,
628 	RX_MSDU_START_RECV_BW_160MHZ,
629 };
630 
631 enum rx_msdu_start_reception_type {
632 	RX_MSDU_START_RECEPTION_TYPE_SU,
633 	RX_MSDU_START_RECEPTION_TYPE_DL_MU_MIMO,
634 	RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA,
635 	RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA_MIMO,
636 	RX_MSDU_START_RECEPTION_TYPE_UL_MU_MIMO,
637 	RX_MSDU_START_RECEPTION_TYPE_UL_MU_OFDMA,
638 	RX_MSDU_START_RECEPTION_TYPE_UL_MU_OFDMA_MIMO,
639 };
640 
641 #define RX_MSDU_START_INFO1_MSDU_LENGTH		GENMASK(13, 0)
642 #define RX_MSDU_START_INFO1_RSVD_1A		BIT(14)
643 #define RX_MSDU_START_INFO1_IPSEC_ESP		BIT(15)
644 #define RX_MSDU_START_INFO1_L3_OFFSET		GENMASK(22, 16)
645 #define RX_MSDU_START_INFO1_IPSEC_AH		BIT(23)
646 #define RX_MSDU_START_INFO1_L4_OFFSET		GENMASK(31, 24)
647 
648 #define RX_MSDU_START_INFO2_MSDU_NUMBER		GENMASK(7, 0)
649 #define RX_MSDU_START_INFO2_DECAP_TYPE		GENMASK(9, 8)
650 #define RX_MSDU_START_INFO2_IPV4		BIT(10)
651 #define RX_MSDU_START_INFO2_IPV6		BIT(11)
652 #define RX_MSDU_START_INFO2_TCP			BIT(12)
653 #define RX_MSDU_START_INFO2_UDP			BIT(13)
654 #define RX_MSDU_START_INFO2_IP_FRAG		BIT(14)
655 #define RX_MSDU_START_INFO2_TCP_ONLY_ACK	BIT(15)
656 #define RX_MSDU_START_INFO2_DA_IS_BCAST_MCAST	BIT(16)
657 #define RX_MSDU_START_INFO2_SELECTED_TOEPLITZ_HASH	GENMASK(18, 17)
658 #define RX_MSDU_START_INFO2_IP_FIXED_HDR_VALID		BIT(19)
659 #define RX_MSDU_START_INFO2_IP_EXTN_HDR_VALID		BIT(20)
660 #define RX_MSDU_START_INFO2_IP_TCP_UDP_HDR_VALID	BIT(21)
661 #define RX_MSDU_START_INFO2_MESH_CTRL_PRESENT		BIT(22)
662 #define RX_MSDU_START_INFO2_LDPC			BIT(23)
663 #define RX_MSDU_START_INFO2_IP4_IP6_NXT_HDR		GENMASK(31, 24)
664 #define RX_MSDU_START_INFO2_DECAP_FORMAT		GENMASK(9, 8)
665 
666 #define RX_MSDU_START_INFO3_USER_RSSI		GENMASK(7, 0)
667 #define RX_MSDU_START_INFO3_PKT_TYPE		GENMASK(11, 8)
668 #define RX_MSDU_START_INFO3_STBC		BIT(12)
669 #define RX_MSDU_START_INFO3_SGI			GENMASK(14, 13)
670 #define RX_MSDU_START_INFO3_RATE_MCS		GENMASK(18, 15)
671 #define RX_MSDU_START_INFO3_RECV_BW		GENMASK(20, 19)
672 #define RX_MSDU_START_INFO3_RECEPTION_TYPE	GENMASK(23, 21)
673 #define RX_MSDU_START_INFO3_MIMO_SS_BITMAP	GENMASK(31, 24)
674 
675 struct rx_msdu_start {
676 	__le16 info0;
677 	__le16 phy_ppdu_id;
678 	__le32 info1;
679 	__le32 info2;
680 	__le32 toeplitz_hash;
681 	__le32 flow_id_toeplitz;
682 	__le32 info3;
683 	__le32 ppdu_start_timestamp;
684 	__le32 phy_meta_data;
685 } __packed;
686 
687 /* rx_msdu_start
688  *
689  * rxpcu_mpdu_filter_in_category
690  *		Field indicates what the reason was that this mpdu frame
691  *		was allowed to come into the receive path by rxpcu. Values
692  *		are defined in enum %RX_DESC_RXPCU_FILTER_*.
693  *
694  * sw_frame_group_id
695  *		SW processes frames based on certain classifications. Values
696  *		are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*.
697  *
698  * phy_ppdu_id
699  *		A ppdu counter value that PHY increments for every PPDU
700  *		received. The counter value wraps around.
701  *
702  * msdu_length
703  *		MSDU length in bytes after decapsulation.
704  *
705  * ipsec_esp
706  *		Set if IPv4/v6 packet is using IPsec ESP.
707  *
708  * l3_offset
709  *		Depending upon mode bit, this field either indicates the
710  *		L3 offset in bytes from the start of the RX_HEADER or the IP
711  *		offset in bytes from the start of the packet after
712  *		decapsulation. The latter is only valid if ipv4_proto or
713  *		ipv6_proto is set.
714  *
715  * ipsec_ah
716  *		Set if IPv4/v6 packet is using IPsec AH
717  *
718  * l4_offset
719  *		Depending upon mode bit, this field either indicates the
720  *		L4 offset nin bytes from the start of RX_HEADER (only valid
721  *		if either ipv4_proto or ipv6_proto is set to 1) or indicates
722  *		the offset in bytes to the start of TCP or UDP header from
723  *		the start of the IP header after decapsulation (Only valid if
724  *		tcp_proto or udp_proto is set). The value 0 indicates that
725  *		the offset is longer than 127 bytes.
726  *
727  * msdu_number
728  *		Indicates the MSDU number within a MPDU.  This value is
729  *		reset to zero at the start of each MPDU.  If the number of
730  *		MSDU exceeds 255 this number will wrap using modulo 256.
731  *
732  * decap_type
733  *		Indicates the format after decapsulation. Values are defined in
734  *		enum %MPDU_START_DECAP_TYPE_*.
735  *
736  * ipv4_proto
737  *		Set if L2 layer indicates IPv4 protocol.
738  *
739  * ipv6_proto
740  *		Set if L2 layer indicates IPv6 protocol.
741  *
742  * tcp_proto
743  *		Set if the ipv4_proto or ipv6_proto are set and the IP protocol
744  *		indicates TCP.
745  *
746  * udp_proto
747  *		Set if the ipv4_proto or ipv6_proto are set and the IP protocol
748  *		indicates UDP.
749  *
750  * ip_frag
751  *		Indicates that either the IP More frag bit is set or IP frag
752  *		number is non-zero.  If set indicates that this is a fragmented
753  *		IP packet.
754  *
755  * tcp_only_ack
756  *		Set if only the TCP Ack bit is set in the TCP flags and if
757  *		the TCP payload is 0.
758  *
759  * da_is_bcast_mcast
760  *		The destination address is broadcast or multicast.
761  *
762  * toeplitz_hash
763  *		Actual chosen Hash.
764  *		0 - Toeplitz hash of 2-tuple (IP source address, IP
765  *		    destination address)
766  *		1 - Toeplitz hash of 4-tuple (IP source	address,
767  *		    IP destination address, L4 (TCP/UDP) source port,
768  *		    L4 (TCP/UDP) destination port)
769  *		2 - Toeplitz of flow_id
770  *		3 - Zero is used
771  *
772  * ip_fixed_header_valid
773  *		Fixed 20-byte IPv4 header or 40-byte IPv6 header parsed
774  *		fully within first 256 bytes of the packet
775  *
776  * ip_extn_header_valid
777  *		IPv6/IPv6 header, including IPv4 options and
778  *		recognizable extension headers parsed fully within first 256
779  *		bytes of the packet
780  *
781  * tcp_udp_header_valid
782  *		Fixed 20-byte TCP (excluding TCP options) or 8-byte UDP
783  *		header parsed fully within first 256 bytes of the packet
784  *
785  * mesh_control_present
786  *		When set, this MSDU includes the 'Mesh Control' field
787  *
788  * ldpc
789  *
790  * ip4_protocol_ip6_next_header
791  *		For IPv4, this is the 8 bit protocol field set). For IPv6 this
792  *		is the 8 bit next_header field.
793  *
794  * toeplitz_hash_2_or_4
795  *		Controlled by RxOLE register - If register bit set to 0,
796  *		Toeplitz hash is computed over 2-tuple IPv4 or IPv6 src/dest
797  *		addresses; otherwise, toeplitz hash is computed over 4-tuple
798  *		IPv4 or IPv6 src/dest addresses and src/dest ports.
799  *
800  * flow_id_toeplitz
801  *		Toeplitz hash of 5-tuple
802  *		{IP source address, IP destination address, IP source port, IP
803  *		destination port, L4 protocol}  in case of non-IPSec.
804  *
805  *		In case of IPSec - Toeplitz hash of 4-tuple
806  *		{IP source address, IP destination address, SPI, L4 protocol}
807  *
808  *		The relevant Toeplitz key registers are provided in RxOLE's
809  *		instance of common parser module. These registers are separate
810  *		from the Toeplitz keys used by ASE/FSE modules inside RxOLE.
811  *		The actual value will be passed on from common parser module
812  *		to RxOLE in one of the WHO_* TLVs.
813  *
814  * user_rssi
815  *		RSSI for this user
816  *
817  * pkt_type
818  *		Values are defined in enum %RX_MSDU_START_PKT_TYPE_*.
819  *
820  * stbc
821  *		When set, use STBC transmission rates.
822  *
823  * sgi
824  *		Field only valid when pkt type is HT, VHT or HE. Values are
825  *		defined in enum %RX_MSDU_START_SGI_*.
826  *
827  * rate_mcs
828  *		MCS Rate used.
829  *
830  * receive_bandwidth
831  *		Full receive Bandwidth. Values are defined in enum
832  *		%RX_MSDU_START_RECV_*.
833  *
834  * reception_type
835  *		Indicates what type of reception this is and defined in enum
836  *		%RX_MSDU_START_RECEPTION_TYPE_*.
837  *
838  * mimo_ss_bitmap
839  *		Field only valid when
840  *		Reception_type is RX_MSDU_START_RECEPTION_TYPE_DL_MU_MIMO or
841  *		RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA_MIMO.
842  *
843  *		Bitmap, with each bit indicating if the related spatial
844  *		stream is used for this STA
845  *
846  *		LSB related to SS 0
847  *
848  *		0 - spatial stream not used for this reception
849  *		1 - spatial stream used for this reception
850  *
851  * ppdu_start_timestamp
852  *		Timestamp that indicates when the PPDU that contained this MPDU
853  *		started on the medium.
854  *
855  * phy_meta_data
856  *		SW programmed Meta data provided by the PHY. Can be used for SW
857  *		to indicate the channel the device is on.
858  */
859 
860 #define RX_MSDU_END_INFO0_RXPCU_MPDU_FITLER	GENMASK(1, 0)
861 #define RX_MSDU_END_INFO0_SW_FRAME_GRP_ID	GENMASK(8, 2)
862 
863 #define RX_MSDU_END_INFO1_KEY_ID		GENMASK(7, 0)
864 #define RX_MSDU_END_INFO1_CCE_SUPER_RULE	GENMASK(13, 8)
865 #define RX_MSDU_END_INFO1_CCND_TRUNCATE		BIT(14)
866 #define RX_MSDU_END_INFO1_CCND_CCE_DIS		BIT(15)
867 #define RX_MSDU_END_INFO1_EXT_WAPI_PN		GENMASK(31, 16)
868 
869 #define RX_MSDU_END_INFO2_REPORTED_MPDU_LEN	GENMASK(13, 0)
870 #define RX_MSDU_END_INFO2_FIRST_MSDU		BIT(14)
871 #define RX_MSDU_END_INFO2_LAST_MSDU		BIT(15)
872 #define RX_MSDU_END_INFO2_SA_IDX_TIMEOUT	BIT(16)
873 #define RX_MSDU_END_INFO2_DA_IDX_TIMEOUT	BIT(17)
874 #define RX_MSDU_END_INFO2_MSDU_LIMIT_ERR	BIT(18)
875 #define RX_MSDU_END_INFO2_FLOW_IDX_TIMEOUT	BIT(19)
876 #define RX_MSDU_END_INFO2_FLOW_IDX_INVALID	BIT(20)
877 #define RX_MSDU_END_INFO2_WIFI_PARSER_ERR	BIT(21)
878 #define RX_MSDU_END_INFO2_AMSDU_PARSET_ERR	BIT(22)
879 #define RX_MSDU_END_INFO2_SA_IS_VALID		BIT(23)
880 #define RX_MSDU_END_INFO2_DA_IS_VALID		BIT(24)
881 #define RX_MSDU_END_INFO2_DA_IS_MCBC		BIT(25)
882 #define RX_MSDU_END_INFO2_L3_HDR_PADDING	GENMASK(27, 26)
883 
884 #define RX_MSDU_END_INFO3_TCP_FLAG		GENMASK(8, 0)
885 #define RX_MSDU_END_INFO3_LRO_ELIGIBLE		BIT(9)
886 
887 #define RX_MSDU_END_INFO4_DA_OFFSET		GENMASK(5, 0)
888 #define RX_MSDU_END_INFO4_SA_OFFSET		GENMASK(11, 6)
889 #define RX_MSDU_END_INFO4_DA_OFFSET_VALID	BIT(12)
890 #define RX_MSDU_END_INFO4_SA_OFFSET_VALID	BIT(13)
891 #define RX_MSDU_END_INFO4_L3_TYPE		GENMASK(31, 16)
892 
893 #define RX_MSDU_END_INFO5_MSDU_DROP		BIT(0)
894 #define RX_MSDU_END_INFO5_REO_DEST_IND		GENMASK(5, 1)
895 #define RX_MSDU_END_INFO5_FLOW_IDX		GENMASK(25, 6)
896 
897 struct rx_msdu_end {
898 	__le16 info0;
899 	__le16 phy_ppdu_id;
900 	__le16 ip_hdr_cksum;
901 	__le16 tcp_udp_cksum;
902 	__le32 info1;
903 	__le32 ext_wapi_pn[2];
904 	__le32 info2;
905 	__le32 ipv6_options_crc;
906 	__le32 tcp_seq_num;
907 	__le32 tcp_ack_num;
908 	__le16 info3;
909 	__le16 window_size;
910 	__le32 info4;
911 	__le32 rule_indication[2];
912 	__le16 sa_idx;
913 	__le16 da_idx;
914 	__le32 info5;
915 	__le32 fse_metadata;
916 	__le16 cce_metadata;
917 	__le16 sa_sw_peer_id;
918 } __packed;
919 
920 /* rx_msdu_end
921  *
922  * rxpcu_mpdu_filter_in_category
923  *		Field indicates what the reason was that this mpdu frame
924  *		was allowed to come into the receive path by rxpcu. Values
925  *		are defined in enum %RX_DESC_RXPCU_FILTER_*.
926  *
927  * sw_frame_group_id
928  *		SW processes frames based on certain classifications. Values
929  *		are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*.
930  *
931  * phy_ppdu_id
932  *		A ppdu counter value that PHY increments for every PPDU
933  *		received. The counter value wraps around.
934  *
935  * ip_hdr_cksum
936  *		This can include the IP header checksum or the pseudo
937  *		header checksum used by TCP/UDP checksum.
938  *
939  * tcp_udp_chksum
940  *		The value of the computed TCP/UDP checksum.  A mode bit
941  *		selects whether this checksum is the full checksum or the
942  *		partial checksum which does not include the pseudo header.
943  *
944  * key_id
945  *		The key ID octet from the IV. Only valid when first_msdu is set.
946  *
947  * cce_super_rule
948  *		Indicates the super filter rule.
949  *
950  * cce_classify_not_done_truncate
951  *		Classification failed due to truncated frame.
952  *
953  * cce_classify_not_done_cce_dis
954  *		Classification failed due to CCE global disable
955  *
956  * ext_wapi_pn*
957  *		Extension PN (packet number) which is only used by WAPI.
958  *
959  * reported_mpdu_length
960  *		MPDU length before decapsulation. Only valid when first_msdu is
961  *		set. This field is taken directly from the length field of the
962  *		A-MPDU delimiter or the preamble length field for non-A-MPDU
963  *		frames.
964  *
965  * first_msdu
966  *		Indicates the first MSDU of A-MSDU. If both first_msdu and
967  *		last_msdu are set in the MSDU then this is a non-aggregated MSDU
968  *		frame: normal MPDU. Interior MSDU in an A-MSDU shall have both
969  *		first_mpdu and last_mpdu bits set to 0.
970  *
971  * last_msdu
972  *		Indicates the last MSDU of the A-MSDU. MPDU end status is only
973  *		valid when last_msdu is set.
974  *
975  * sa_idx_timeout
976  *		Indicates an unsuccessful MAC source address search due to the
977  *		expiring of the search timer.
978  *
979  * da_idx_timeout
980  *		Indicates an unsuccessful MAC destination address search due to
981  *		the expiring of the search timer.
982  *
983  * msdu_limit_error
984  *		Indicates that the MSDU threshold was exceeded and thus all the
985  *		rest of the MSDUs will not be scattered and will not be
986  *		decapsulated but will be DMA'ed in RAW format as a single MSDU.
987  *
988  * flow_idx_timeout
989  *		Indicates an unsuccessful flow search due to the expiring of
990  *		the search timer.
991  *
992  * flow_idx_invalid
993  *		flow id is not valid.
994  *
995  * amsdu_parser_error
996  *		A-MSDU could not be properly de-agregated.
997  *
998  * sa_is_valid
999  *		Indicates that OLE found a valid SA entry.
1000  *
1001  * da_is_valid
1002  *		Indicates that OLE found a valid DA entry.
1003  *
1004  * da_is_mcbc
1005  *		Field Only valid if da_is_valid is set. Indicates the DA address
1006  *		was a Multicast of Broadcast address.
1007  *
1008  * l3_header_padding
1009  *		Number of bytes padded  to make sure that the L3 header will
1010  *		always start of a Dword boundary.
1011  *
1012  * ipv6_options_crc
1013  *		32 bit CRC computed out of  IP v6 extension headers.
1014  *
1015  * tcp_seq_number
1016  *		TCP sequence number.
1017  *
1018  * tcp_ack_number
1019  *		TCP acknowledge number.
1020  *
1021  * tcp_flag
1022  *		TCP flags {NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN}.
1023  *
1024  * lro_eligible
1025  *		Computed out of TCP and IP fields to indicate that this
1026  *		MSDU is eligible for LRO.
1027  *
1028  * window_size
1029  *		TCP receive window size.
1030  *
1031  * da_offset
1032  *		Offset into MSDU buffer for DA.
1033  *
1034  * sa_offset
1035  *		Offset into MSDU buffer for SA.
1036  *
1037  * da_offset_valid
1038  *		da_offset field is valid. This will be set to 0 in case
1039  *		of a dynamic A-MSDU when DA is compressed.
1040  *
1041  * sa_offset_valid
1042  *		sa_offset field is valid. This will be set to 0 in case
1043  *		of a dynamic A-MSDU when SA is compressed.
1044  *
1045  * l3_type
1046  *		The 16-bit type value indicating the type of L3 later
1047  *		extracted from LLC/SNAP, set to zero if SNAP is not
1048  *		available.
1049  *
1050  * rule_indication
1051  *		Bitmap indicating which of rules have matched.
1052  *
1053  * sa_idx
1054  *		The offset in the address table which matches MAC source address
1055  *
1056  * da_idx
1057  *		The offset in the address table which matches MAC destination
1058  *		address.
1059  *
1060  * msdu_drop
1061  *		REO shall drop this MSDU and not forward it to any other ring.
1062  *
1063  * reo_destination_indication
1064  *		The id of the reo exit ring where the msdu frame shall push
1065  *		after (MPDU level) reordering has finished. Values are defined
1066  *		in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_.
1067  *
1068  * flow_idx
1069  *		Flow table index.
1070  *
1071  * fse_metadata
1072  *		FSE related meta data.
1073  *
1074  * cce_metadata
1075  *		CCE related meta data.
1076  *
1077  * sa_sw_peer_id
1078  *		sw_peer_id from the address search entry corresponding to the
1079  *		source address of the MSDU.
1080  */
1081 
1082 enum rx_mpdu_end_rxdma_dest_ring {
1083 	RX_MPDU_END_RXDMA_DEST_RING_RELEASE,
1084 	RX_MPDU_END_RXDMA_DEST_RING_FW,
1085 	RX_MPDU_END_RXDMA_DEST_RING_SW,
1086 	RX_MPDU_END_RXDMA_DEST_RING_REO,
1087 };
1088 
1089 #define RX_MPDU_END_INFO1_UNSUP_KTYPE_SHORT_FRAME	BIT(11)
1090 #define RX_MPDU_END_INFO1_RX_IN_TX_DECRYPT_BYT		BIT(12)
1091 #define RX_MPDU_END_INFO1_OVERFLOW_ERR			BIT(13)
1092 #define RX_MPDU_END_INFO1_MPDU_LEN_ERR			BIT(14)
1093 #define RX_MPDU_END_INFO1_TKIP_MIC_ERR			BIT(15)
1094 #define RX_MPDU_END_INFO1_DECRYPT_ERR			BIT(16)
1095 #define RX_MPDU_END_INFO1_UNENCRYPTED_FRAME_ERR		BIT(17)
1096 #define RX_MPDU_END_INFO1_PN_FIELDS_VALID		BIT(18)
1097 #define RX_MPDU_END_INFO1_FCS_ERR			BIT(19)
1098 #define RX_MPDU_END_INFO1_MSDU_LEN_ERR			BIT(20)
1099 #define RX_MPDU_END_INFO1_RXDMA0_DEST_RING		GENMASK(22, 21)
1100 #define RX_MPDU_END_INFO1_RXDMA1_DEST_RING		GENMASK(24, 23)
1101 #define RX_MPDU_END_INFO1_DECRYPT_STATUS_CODE		GENMASK(27, 25)
1102 #define RX_MPDU_END_INFO1_RX_BITMAP_NOT_UPD		BIT(28)
1103 
1104 struct rx_mpdu_end {
1105 	__le16 info0;
1106 	__le16 phy_ppdu_id;
1107 	__le32 info1;
1108 } __packed;
1109 
1110 /* rx_mpdu_end
1111  *
1112  * rxpcu_mpdu_filter_in_category
1113  *		Field indicates what the reason was that this mpdu frame
1114  *		was allowed to come into the receive path by rxpcu. Values
1115  *		are defined in enum %RX_DESC_RXPCU_FILTER_*.
1116  *
1117  * sw_frame_group_id
1118  *		SW processes frames based on certain classifications. Values
1119  *		are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*.
1120  *
1121  * phy_ppdu_id
1122  *		A ppdu counter value that PHY increments for every PPDU
1123  *		received. The counter value wraps around.
1124  *
1125  * unsup_ktype_short_frame
1126  *		This bit will be '1' when WEP or TKIP or WAPI key type is
1127  *		received for 11ah short frame. Crypto will bypass the received
1128  *		packet without decryption to RxOLE after setting this bit.
1129  *
1130  * rx_in_tx_decrypt_byp
1131  *		Indicates that RX packet is not decrypted as Crypto is
1132  *		busy with TX packet processing.
1133  *
1134  * overflow_err
1135  *		RXPCU Receive FIFO ran out of space to receive the full MPDU.
1136  *		Therefore this MPDU is terminated early and is thus corrupted.
1137  *
1138  *		This MPDU will not be ACKed.
1139  *
1140  *		RXPCU might still be able to correctly receive the following
1141  *		MPDUs in the PPDU if enough fifo space became available in time.
1142  *
1143  * mpdu_length_err
1144  *		Set by RXPCU if the expected MPDU length does not correspond
1145  *		with the actually received number of bytes in the MPDU.
1146  *
1147  * tkip_mic_err
1148  *		Set by Rx crypto when crypto detected a TKIP MIC error for
1149  *		this MPDU.
1150  *
1151  * decrypt_err
1152  *		Set by RX CRYPTO when CRYPTO detected a decrypt error for this
1153  *		MPDU or CRYPTO received an encrypted frame, but did not get a
1154  *		valid corresponding key id in the peer entry.
1155  *
1156  * unencrypted_frame_err
1157  *		Set by RX CRYPTO when CRYPTO detected an unencrypted frame while
1158  *		in the peer entry field 'All_frames_shall_be_encrypted' is set.
1159  *
1160  * pn_fields_contain_valid_info
1161  *		Set by RX CRYPTO to indicate that there is a valid PN field
1162  *		present in this MPDU.
1163  *
1164  * fcs_err
1165  *		Set by RXPCU when there is an FCS error detected for this MPDU.
1166  *
1167  * msdu_length_err
1168  *		Set by RXOLE when there is an msdu length error detected
1169  *		in at least 1 of the MSDUs embedded within the MPDU.
1170  *
1171  * rxdma0_destination_ring
1172  * rxdma1_destination_ring
1173  *		The ring to which RXDMA0/1 shall push the frame, assuming
1174  *		no MPDU level errors are detected. In case of MPDU level
1175  *		errors, RXDMA0/1 might change the RXDMA0/1 destination. Values
1176  *		are defined in %enum RX_MPDU_END_RXDMA_DEST_RING_*.
1177  *
1178  * decrypt_status_code
1179  *		Field provides insight into the decryption performed. Values
1180  *		are defined in enum %RX_DESC_DECRYPT_STATUS_CODE_*.
1181  *
1182  * rx_bitmap_not_updated
1183  *		Frame is received, but RXPCU could not update the receive bitmap
1184  *		due to (temporary) fifo constraints.
1185  */
1186 
1187 /* Padding bytes to avoid TLV's spanning across 128 byte boundary */
1188 #define HAL_RX_DESC_PADDING0_BYTES	4
1189 #define HAL_RX_DESC_PADDING1_BYTES	16
1190 
1191 #define HAL_RX_DESC_HDR_STATUS_LEN	120
1192 
1193 struct hal_rx_desc {
1194 	__le32 msdu_end_tag;
1195 	struct rx_msdu_end msdu_end;
1196 	__le32 rx_attn_tag;
1197 	struct rx_attention attention;
1198 	__le32 msdu_start_tag;
1199 	struct rx_msdu_start msdu_start;
1200 	u8 rx_padding0[HAL_RX_DESC_PADDING0_BYTES];
1201 	__le32 mpdu_start_tag;
1202 	struct rx_mpdu_start mpdu_start;
1203 	__le32 mpdu_end_tag;
1204 	struct rx_mpdu_end mpdu_end;
1205 	u8 rx_padding1[HAL_RX_DESC_PADDING1_BYTES];
1206 	__le32 hdr_status_tag;
1207 	__le32 phy_ppdu_id;
1208 	u8 hdr_status[HAL_RX_DESC_HDR_STATUS_LEN];
1209 	u8 msdu_payload[0];
1210 } __packed;
1211 
1212 #define HAL_RX_RU_ALLOC_TYPE_MAX 6
1213 #define RU_26  1
1214 #define RU_52  2
1215 #define RU_106 4
1216 #define RU_242 9
1217 #define RU_484 18
1218 #define RU_996 37
1219 
1220 #endif /* ATH11K_RX_DESC_H */
1221