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1 /******************************************************************************
2  *
3  * This file is provided under a dual BSD/GPLv2 license.  When using or
4  * redistributing this file, you may do so under either license.
5  *
6  * GPL LICENSE SUMMARY
7  *
8  * Copyright(c) 2012 - 2014, 2018 - 2020 Intel Corporation. All rights reserved.
9  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10  * Copyright(c) 2015 - 2017 Intel Deutschland GmbH
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of version 2 of the GNU General Public License as
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17  * WITHOUT ANY WARRANTY; without even the implied warranty of
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19  * General Public License for more details.
20  *
21  * The full GNU General Public License is included in this distribution
22  * in the file called COPYING.
23  *
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25  *  Intel Linux Wireless <linuxwifi@intel.com>
26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27  *
28  * BSD LICENSE
29  *
30  * Copyright(c) 2012 - 2014, 2018 - 2020 Intel Corporation. All rights reserved.
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32  * Copyright(c) 2015 - 2017 Intel Deutschland GmbH
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62 
63 #ifndef __iwl_fw_api_rx_h__
64 #define __iwl_fw_api_rx_h__
65 
66 /* API for pre-9000 hardware */
67 
68 #define IWL_RX_INFO_PHY_CNT 8
69 #define IWL_RX_INFO_ENERGY_ANT_ABC_IDX 1
70 #define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
71 #define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
72 #define IWL_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000
73 #define IWL_RX_INFO_ENERGY_ANT_A_POS 0
74 #define IWL_RX_INFO_ENERGY_ANT_B_POS 8
75 #define IWL_RX_INFO_ENERGY_ANT_C_POS 16
76 
77 enum iwl_mac_context_info {
78 	MAC_CONTEXT_INFO_NONE,
79 	MAC_CONTEXT_INFO_GSCAN,
80 };
81 
82 /**
83  * struct iwl_rx_phy_info - phy info
84  * (REPLY_RX_PHY_CMD = 0xc0)
85  * @non_cfg_phy_cnt: non configurable DSP phy data byte count
86  * @cfg_phy_cnt: configurable DSP phy data byte count
87  * @stat_id: configurable DSP phy data set ID
88  * @reserved1: reserved
89  * @system_timestamp: GP2  at on air rise
90  * @timestamp: TSF at on air rise
91  * @beacon_time_stamp: beacon at on-air rise
92  * @phy_flags: general phy flags: band, modulation, ...
93  * @channel: channel number
94  * @non_cfg_phy: for various implementations of non_cfg_phy
95  * @rate_n_flags: RATE_MCS_*
96  * @byte_count: frame's byte-count
97  * @frame_time: frame's time on the air, based on byte count and frame rate
98  *	calculation
99  * @mac_active_msk: what MACs were active when the frame was received
100  * @mac_context_info: additional info on the context in which the frame was
101  *	received as defined in &enum iwl_mac_context_info
102  *
103  * Before each Rx, the device sends this data. It contains PHY information
104  * about the reception of the packet.
105  */
106 struct iwl_rx_phy_info {
107 	u8 non_cfg_phy_cnt;
108 	u8 cfg_phy_cnt;
109 	u8 stat_id;
110 	u8 reserved1;
111 	__le32 system_timestamp;
112 	__le64 timestamp;
113 	__le32 beacon_time_stamp;
114 	__le16 phy_flags;
115 	__le16 channel;
116 	__le32 non_cfg_phy[IWL_RX_INFO_PHY_CNT];
117 	__le32 rate_n_flags;
118 	__le32 byte_count;
119 	u8 mac_active_msk;
120 	u8 mac_context_info;
121 	__le16 frame_time;
122 } __packed;
123 
124 /*
125  * TCP offload Rx assist info
126  *
127  * bits 0:3 - reserved
128  * bits 4:7 - MIC CRC length
129  * bits 8:12 - MAC header length
130  * bit 13 - Padding indication
131  * bit 14 - A-AMSDU indication
132  * bit 15 - Offload enabled
133  */
134 enum iwl_csum_rx_assist_info {
135 	CSUM_RXA_RESERVED_MASK	= 0x000f,
136 	CSUM_RXA_MICSIZE_MASK	= 0x00f0,
137 	CSUM_RXA_HEADERLEN_MASK	= 0x1f00,
138 	CSUM_RXA_PADD		= BIT(13),
139 	CSUM_RXA_AMSDU		= BIT(14),
140 	CSUM_RXA_ENA		= BIT(15)
141 };
142 
143 /**
144  * struct iwl_rx_mpdu_res_start - phy info
145  * @byte_count: byte count of the frame
146  * @assist: see &enum iwl_csum_rx_assist_info
147  */
148 struct iwl_rx_mpdu_res_start {
149 	__le16 byte_count;
150 	__le16 assist;
151 } __packed; /* _RX_MPDU_RES_START_API_S_VER_2 */
152 
153 /**
154  * enum iwl_rx_phy_flags - to parse %iwl_rx_phy_info phy_flags
155  * @RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band
156  * @RX_RES_PHY_FLAGS_MOD_CCK: modulation is CCK
157  * @RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short
158  * @RX_RES_PHY_FLAGS_NARROW_BAND: narrow band (<20 MHz) receive
159  * @RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received
160  * @RX_RES_PHY_FLAGS_ANTENNA_POS: antenna bit position
161  * @RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU
162  * @RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame
163  * @RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble
164  * @RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame
165  */
166 enum iwl_rx_phy_flags {
167 	RX_RES_PHY_FLAGS_BAND_24	= BIT(0),
168 	RX_RES_PHY_FLAGS_MOD_CCK	= BIT(1),
169 	RX_RES_PHY_FLAGS_SHORT_PREAMBLE	= BIT(2),
170 	RX_RES_PHY_FLAGS_NARROW_BAND	= BIT(3),
171 	RX_RES_PHY_FLAGS_ANTENNA	= (0x7 << 4),
172 	RX_RES_PHY_FLAGS_ANTENNA_POS	= 4,
173 	RX_RES_PHY_FLAGS_AGG		= BIT(7),
174 	RX_RES_PHY_FLAGS_OFDM_HT	= BIT(8),
175 	RX_RES_PHY_FLAGS_OFDM_GF	= BIT(9),
176 	RX_RES_PHY_FLAGS_OFDM_VHT	= BIT(10),
177 };
178 
179 /**
180  * enum iwl_mvm_rx_status - written by fw for each Rx packet
181  * @RX_MPDU_RES_STATUS_CRC_OK: CRC is fine
182  * @RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow
183  * @RX_MPDU_RES_STATUS_SRC_STA_FOUND: station was found
184  * @RX_MPDU_RES_STATUS_KEY_VALID: key was valid
185  * @RX_MPDU_RES_STATUS_KEY_PARAM_OK: key parameters were usable
186  * @RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed
187  * @RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked
188  *	in the driver.
189  * @RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine
190  * @RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR:  valid for alg = CCM_CMAC or
191  *	alg = CCM only. Checks replay attack for 11w frames. Relevant only if
192  *	%RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set.
193  * @RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted
194  * @RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP
195  * @RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM
196  * @RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP
197  * @RX_MPDU_RES_STATUS_SEC_EXT_ENC: this frame is encrypted using extension
198  *	algorithm
199  * @RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC
200  * @RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted
201  * @RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm
202  * @RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted
203  * @RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: extended IV (set with TKIP)
204  * @RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: key ID comparison done
205  * @RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame
206  * @RX_MPDU_RES_STATUS_CSUM_DONE: checksum was done by the hw
207  * @RX_MPDU_RES_STATUS_CSUM_OK: checksum found no errors
208  * @RX_MPDU_RES_STATUS_STA_ID_MSK: station ID mask
209  * @RX_MDPU_RES_STATUS_STA_ID_SHIFT: station ID bit shift
210  */
211 enum iwl_mvm_rx_status {
212 	RX_MPDU_RES_STATUS_CRC_OK			= BIT(0),
213 	RX_MPDU_RES_STATUS_OVERRUN_OK			= BIT(1),
214 	RX_MPDU_RES_STATUS_SRC_STA_FOUND		= BIT(2),
215 	RX_MPDU_RES_STATUS_KEY_VALID			= BIT(3),
216 	RX_MPDU_RES_STATUS_KEY_PARAM_OK			= BIT(4),
217 	RX_MPDU_RES_STATUS_ICV_OK			= BIT(5),
218 	RX_MPDU_RES_STATUS_MIC_OK			= BIT(6),
219 	RX_MPDU_RES_STATUS_TTAK_OK			= BIT(7),
220 	RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR		= BIT(7),
221 	RX_MPDU_RES_STATUS_SEC_NO_ENC			= (0 << 8),
222 	RX_MPDU_RES_STATUS_SEC_WEP_ENC			= (1 << 8),
223 	RX_MPDU_RES_STATUS_SEC_CCM_ENC			= (2 << 8),
224 	RX_MPDU_RES_STATUS_SEC_TKIP_ENC			= (3 << 8),
225 	RX_MPDU_RES_STATUS_SEC_EXT_ENC			= (4 << 8),
226 	RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC		= (6 << 8),
227 	RX_MPDU_RES_STATUS_SEC_ENC_ERR			= (7 << 8),
228 	RX_MPDU_RES_STATUS_SEC_ENC_MSK			= (7 << 8),
229 	RX_MPDU_RES_STATUS_DEC_DONE			= BIT(11),
230 	RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP		= BIT(13),
231 	RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT		= BIT(14),
232 	RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME		= BIT(15),
233 	RX_MPDU_RES_STATUS_CSUM_DONE			= BIT(16),
234 	RX_MPDU_RES_STATUS_CSUM_OK			= BIT(17),
235 	RX_MDPU_RES_STATUS_STA_ID_SHIFT			= 24,
236 	RX_MPDU_RES_STATUS_STA_ID_MSK			= 0x1f << RX_MDPU_RES_STATUS_STA_ID_SHIFT,
237 };
238 
239 /* 9000 series API */
240 enum iwl_rx_mpdu_mac_flags1 {
241 	IWL_RX_MDPU_MFLG1_ADDRTYPE_MASK		= 0x03,
242 	IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK	= 0xf0,
243 	/* shift should be 4, but the length is measured in 2-byte
244 	 * words, so shifting only by 3 gives a byte result
245 	 */
246 	IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT	= 3,
247 };
248 
249 enum iwl_rx_mpdu_mac_flags2 {
250 	/* in 2-byte words */
251 	IWL_RX_MPDU_MFLG2_HDR_LEN_MASK		= 0x1f,
252 	IWL_RX_MPDU_MFLG2_PAD			= 0x20,
253 	IWL_RX_MPDU_MFLG2_AMSDU			= 0x40,
254 };
255 
256 enum iwl_rx_mpdu_amsdu_info {
257 	IWL_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK	= 0x7f,
258 	IWL_RX_MPDU_AMSDU_LAST_SUBFRAME		= 0x80,
259 };
260 
261 #define RX_MPDU_BAND_POS 6
262 #define RX_MPDU_BAND_MASK 0xC0
263 #define BAND_IN_RX_STATUS(_val) \
264 	(((_val) & RX_MPDU_BAND_MASK) >> RX_MPDU_BAND_POS)
265 
266 enum iwl_rx_l3_proto_values {
267 	IWL_RX_L3_TYPE_NONE,
268 	IWL_RX_L3_TYPE_IPV4,
269 	IWL_RX_L3_TYPE_IPV4_FRAG,
270 	IWL_RX_L3_TYPE_IPV6_FRAG,
271 	IWL_RX_L3_TYPE_IPV6,
272 	IWL_RX_L3_TYPE_IPV6_IN_IPV4,
273 	IWL_RX_L3_TYPE_ARP,
274 	IWL_RX_L3_TYPE_EAPOL,
275 };
276 
277 #define IWL_RX_L3_PROTO_POS 4
278 
279 enum iwl_rx_l3l4_flags {
280 	IWL_RX_L3L4_IP_HDR_CSUM_OK		= BIT(0),
281 	IWL_RX_L3L4_TCP_UDP_CSUM_OK		= BIT(1),
282 	IWL_RX_L3L4_TCP_FIN_SYN_RST_PSH		= BIT(2),
283 	IWL_RX_L3L4_TCP_ACK			= BIT(3),
284 	IWL_RX_L3L4_L3_PROTO_MASK		= 0xf << IWL_RX_L3_PROTO_POS,
285 	IWL_RX_L3L4_L4_PROTO_MASK		= 0xf << 8,
286 	IWL_RX_L3L4_RSS_HASH_MASK		= 0xf << 12,
287 };
288 
289 enum iwl_rx_mpdu_status {
290 	IWL_RX_MPDU_STATUS_CRC_OK		= BIT(0),
291 	IWL_RX_MPDU_STATUS_OVERRUN_OK		= BIT(1),
292 	IWL_RX_MPDU_STATUS_SRC_STA_FOUND	= BIT(2),
293 	IWL_RX_MPDU_STATUS_KEY_VALID		= BIT(3),
294 	IWL_RX_MPDU_STATUS_KEY_PARAM_OK		= BIT(4),
295 	IWL_RX_MPDU_STATUS_ICV_OK		= BIT(5),
296 	IWL_RX_MPDU_STATUS_MIC_OK		= BIT(6),
297 	IWL_RX_MPDU_RES_STATUS_TTAK_OK		= BIT(7),
298 	IWL_RX_MPDU_STATUS_SEC_MASK		= 0x7 << 8,
299 	IWL_RX_MPDU_STATUS_SEC_UNKNOWN		= IWL_RX_MPDU_STATUS_SEC_MASK,
300 	IWL_RX_MPDU_STATUS_SEC_NONE		= 0x0 << 8,
301 	IWL_RX_MPDU_STATUS_SEC_WEP		= 0x1 << 8,
302 	IWL_RX_MPDU_STATUS_SEC_CCM		= 0x2 << 8,
303 	IWL_RX_MPDU_STATUS_SEC_TKIP		= 0x3 << 8,
304 	IWL_RX_MPDU_STATUS_SEC_EXT_ENC		= 0x4 << 8,
305 	IWL_RX_MPDU_STATUS_SEC_GCM		= 0x5 << 8,
306 	IWL_RX_MPDU_STATUS_DECRYPTED		= BIT(11),
307 	IWL_RX_MPDU_STATUS_WEP_MATCH		= BIT(12),
308 	IWL_RX_MPDU_STATUS_EXT_IV_MATCH		= BIT(13),
309 	IWL_RX_MPDU_STATUS_KEY_ID_MATCH		= BIT(14),
310 	IWL_RX_MPDU_STATUS_ROBUST_MNG_FRAME	= BIT(15),
311 
312 	IWL_RX_MPDU_STATUS_KEY			= 0x3f0000,
313 	IWL_RX_MPDU_STATUS_DUPLICATE		= BIT(22),
314 
315 	IWL_RX_MPDU_STATUS_STA_ID		= 0x1f000000,
316 };
317 
318 #define IWL_RX_REORDER_DATA_INVALID_BAID 0x7f
319 
320 enum iwl_rx_mpdu_reorder_data {
321 	IWL_RX_MPDU_REORDER_NSSN_MASK		= 0x00000fff,
322 	IWL_RX_MPDU_REORDER_SN_MASK		= 0x00fff000,
323 	IWL_RX_MPDU_REORDER_SN_SHIFT		= 12,
324 	IWL_RX_MPDU_REORDER_BAID_MASK		= 0x7f000000,
325 	IWL_RX_MPDU_REORDER_BAID_SHIFT		= 24,
326 	IWL_RX_MPDU_REORDER_BA_OLD_SN		= 0x80000000,
327 };
328 
329 enum iwl_rx_mpdu_phy_info {
330 	IWL_RX_MPDU_PHY_AMPDU		= BIT(5),
331 	IWL_RX_MPDU_PHY_AMPDU_TOGGLE	= BIT(6),
332 	IWL_RX_MPDU_PHY_SHORT_PREAMBLE	= BIT(7),
333 	/* short preamble is only for CCK, for non-CCK overridden by this */
334 	IWL_RX_MPDU_PHY_NCCK_ADDTL_NTFY	= BIT(7),
335 	IWL_RX_MPDU_PHY_TSF_OVERLOAD	= BIT(8),
336 };
337 
338 enum iwl_rx_mpdu_mac_info {
339 	IWL_RX_MPDU_PHY_MAC_INDEX_MASK		= 0x0f,
340 	IWL_RX_MPDU_PHY_PHY_INDEX_MASK		= 0xf0,
341 };
342 
343 /* TSF overload low dword */
344 enum iwl_rx_phy_data0 {
345 	/* info type: HE any */
346 	IWL_RX_PHY_DATA0_HE_BEAM_CHNG				= 0x00000001,
347 	IWL_RX_PHY_DATA0_HE_UPLINK				= 0x00000002,
348 	IWL_RX_PHY_DATA0_HE_BSS_COLOR_MASK			= 0x000000fc,
349 	IWL_RX_PHY_DATA0_HE_SPATIAL_REUSE_MASK			= 0x00000f00,
350 	/* 1 bit reserved */
351 	IWL_RX_PHY_DATA0_HE_TXOP_DUR_MASK			= 0x000fe000,
352 	IWL_RX_PHY_DATA0_HE_LDPC_EXT_SYM			= 0x00100000,
353 	IWL_RX_PHY_DATA0_HE_PRE_FEC_PAD_MASK			= 0x00600000,
354 	IWL_RX_PHY_DATA0_HE_PE_DISAMBIG				= 0x00800000,
355 	IWL_RX_PHY_DATA0_HE_DOPPLER				= 0x01000000,
356 	/* 6 bits reserved */
357 	IWL_RX_PHY_DATA0_HE_DELIM_EOF				= 0x80000000,
358 };
359 
360 enum iwl_rx_phy_info_type {
361 	IWL_RX_PHY_INFO_TYPE_NONE				= 0,
362 	IWL_RX_PHY_INFO_TYPE_CCK				= 1,
363 	IWL_RX_PHY_INFO_TYPE_OFDM_LGCY				= 2,
364 	IWL_RX_PHY_INFO_TYPE_HT					= 3,
365 	IWL_RX_PHY_INFO_TYPE_VHT_SU				= 4,
366 	IWL_RX_PHY_INFO_TYPE_VHT_MU				= 5,
367 	IWL_RX_PHY_INFO_TYPE_HE_SU				= 6,
368 	IWL_RX_PHY_INFO_TYPE_HE_MU				= 7,
369 	IWL_RX_PHY_INFO_TYPE_HE_TB				= 8,
370 	IWL_RX_PHY_INFO_TYPE_HE_MU_EXT				= 9,
371 	IWL_RX_PHY_INFO_TYPE_HE_TB_EXT				= 10,
372 };
373 
374 /* TSF overload high dword */
375 enum iwl_rx_phy_data1 {
376 	/*
377 	 * check this first - if TSF overload is set,
378 	 * see &enum iwl_rx_phy_info_type
379 	 */
380 	IWL_RX_PHY_DATA1_INFO_TYPE_MASK				= 0xf0000000,
381 
382 	/* info type: HT/VHT/HE any */
383 	IWL_RX_PHY_DATA1_LSIG_LEN_MASK				= 0x0fff0000,
384 
385 	/* info type: HE MU/MU-EXT */
386 	IWL_RX_PHY_DATA1_HE_MU_SIGB_COMPRESSION			= 0x00000001,
387 	IWL_RX_PHY_DATA1_HE_MU_SIBG_SYM_OR_USER_NUM_MASK	= 0x0000001e,
388 
389 	/* info type: HE any */
390 	IWL_RX_PHY_DATA1_HE_LTF_NUM_MASK			= 0x000000e0,
391 	IWL_RX_PHY_DATA1_HE_RU_ALLOC_SEC80			= 0x00000100,
392 	/* trigger encoded */
393 	IWL_RX_PHY_DATA1_HE_RU_ALLOC_MASK			= 0x0000fe00,
394 
395 	/* info type: HE TB/TX-EXT */
396 	IWL_RX_PHY_DATA1_HE_TB_PILOT_TYPE			= 0x00000001,
397 	IWL_RX_PHY_DATA1_HE_TB_LOW_SS_MASK			= 0x0000000e,
398 };
399 
400 /* goes into Metadata DW 7 */
401 enum iwl_rx_phy_data2 {
402 	/* info type: HE MU-EXT */
403 	/* the a1/a2/... is what the PHY/firmware calls the values */
404 	IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU0		= 0x000000ff, /* a1 */
405 	IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU2		= 0x0000ff00, /* a2 */
406 	IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU0		= 0x00ff0000, /* b1 */
407 	IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU2		= 0xff000000, /* b2 */
408 
409 	/* info type: HE TB-EXT */
410 	IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE1		= 0x0000000f,
411 	IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE2		= 0x000000f0,
412 	IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE3		= 0x00000f00,
413 	IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE4		= 0x0000f000,
414 };
415 
416 /* goes into Metadata DW 8 */
417 enum iwl_rx_phy_data3 {
418 	/* info type: HE MU-EXT */
419 	IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU1		= 0x000000ff, /* c1 */
420 	IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU3		= 0x0000ff00, /* c2 */
421 	IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU1		= 0x00ff0000, /* d1 */
422 	IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU3		= 0xff000000, /* d2 */
423 };
424 
425 /* goes into Metadata DW 4 high 16 bits */
426 enum iwl_rx_phy_data4 {
427 	/* info type: HE MU-EXT */
428 	IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CTR_RU			= 0x0001,
429 	IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CTR_RU			= 0x0002,
430 	IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CRC_OK			= 0x0004,
431 	IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CRC_OK			= 0x0008,
432 	IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_MCS_MASK		= 0x00f0,
433 	IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_DCM			= 0x0100,
434 	IWL_RX_PHY_DATA4_HE_MU_EXT_PREAMBLE_PUNC_TYPE_MASK	= 0x0600,
435 };
436 
437 /**
438  * struct iwl_rx_mpdu_desc_v1 - RX MPDU descriptor
439  */
440 struct iwl_rx_mpdu_desc_v1 {
441 	/* DW7 - carries rss_hash only when rpa_en == 1 */
442 	union {
443 		/**
444 		 * @rss_hash: RSS hash value
445 		 */
446 		__le32 rss_hash;
447 
448 		/**
449 		 * @phy_data2: depends on info type (see @phy_data1)
450 		 */
451 		__le32 phy_data2;
452 	};
453 
454 	/* DW8 - carries filter_match only when rpa_en == 1 */
455 	union {
456 		/**
457 		 * @filter_match: filter match value
458 		 */
459 		__le32 filter_match;
460 
461 		/**
462 		 * @phy_data3: depends on info type (see @phy_data1)
463 		 */
464 		__le32 phy_data3;
465 	};
466 
467 	/* DW9 */
468 	/**
469 	 * @rate_n_flags: RX rate/flags encoding
470 	 */
471 	__le32 rate_n_flags;
472 	/* DW10 */
473 	/**
474 	 * @energy_a: energy chain A
475 	 */
476 	u8 energy_a;
477 	/**
478 	 * @energy_b: energy chain B
479 	 */
480 	u8 energy_b;
481 	/**
482 	 * @channel: channel number
483 	 */
484 	u8 channel;
485 	/**
486 	 * @mac_context: MAC context mask
487 	 */
488 	u8 mac_context;
489 	/* DW11 */
490 	/**
491 	 * @gp2_on_air_rise: GP2 timer value on air rise (INA)
492 	 */
493 	__le32 gp2_on_air_rise;
494 	/* DW12 & DW13 */
495 	union {
496 		/**
497 		 * @tsf_on_air_rise:
498 		 * TSF value on air rise (INA), only valid if
499 		 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set
500 		 */
501 		__le64 tsf_on_air_rise;
502 
503 		struct {
504 			/**
505 			 * @phy_data0: depends on info_type, see @phy_data1
506 			 */
507 			__le32 phy_data0;
508 			/**
509 			 * @phy_data1: valid only if
510 			 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set,
511 			 * see &enum iwl_rx_phy_data1.
512 			 */
513 			__le32 phy_data1;
514 		};
515 	};
516 } __packed;
517 
518 /**
519  * struct iwl_rx_mpdu_desc_v3 - RX MPDU descriptor
520  */
521 struct iwl_rx_mpdu_desc_v3 {
522 	/* DW7 - carries filter_match only when rpa_en == 1 */
523 	union {
524 		/**
525 		 * @filter_match: filter match value
526 		 */
527 		__le32 filter_match;
528 
529 		/**
530 		 * @phy_data3: depends on info type (see @phy_data1)
531 		 */
532 		__le32 phy_data3;
533 	};
534 
535 	/* DW8 - carries rss_hash only when rpa_en == 1 */
536 	union {
537 		/**
538 		 * @rss_hash: RSS hash value
539 		 */
540 		__le32 rss_hash;
541 
542 		/**
543 		 * @phy_data2: depends on info type (see @phy_data1)
544 		 */
545 		__le32 phy_data2;
546 	};
547 	/* DW9 */
548 	/**
549 	 * @partial_hash: 31:0 ip/tcp header hash
550 	 *	w/o some fields (such as IP SRC addr)
551 	 */
552 	__le32 partial_hash;
553 	/* DW10 */
554 	/**
555 	 * @raw_xsum: raw xsum value
556 	 */
557 	__be16 raw_xsum;
558 	/**
559 	 * @reserved_xsum: reserved high bits in the raw checksum
560 	 */
561 	__le16 reserved_xsum;
562 	/* DW11 */
563 	/**
564 	 * @rate_n_flags: RX rate/flags encoding
565 	 */
566 	__le32 rate_n_flags;
567 	/* DW12 */
568 	/**
569 	 * @energy_a: energy chain A
570 	 */
571 	u8 energy_a;
572 	/**
573 	 * @energy_b: energy chain B
574 	 */
575 	u8 energy_b;
576 	/**
577 	 * @channel: channel number
578 	 */
579 	u8 channel;
580 	/**
581 	 * @mac_context: MAC context mask
582 	 */
583 	u8 mac_context;
584 	/* DW13 */
585 	/**
586 	 * @gp2_on_air_rise: GP2 timer value on air rise (INA)
587 	 */
588 	__le32 gp2_on_air_rise;
589 	/* DW14 & DW15 */
590 	union {
591 		/**
592 		 * @tsf_on_air_rise:
593 		 * TSF value on air rise (INA), only valid if
594 		 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set
595 		 */
596 		__le64 tsf_on_air_rise;
597 
598 		struct {
599 			/**
600 			 * @phy_data0: depends on info_type, see @phy_data1
601 			 */
602 			__le32 phy_data0;
603 			/**
604 			 * @phy_data1: valid only if
605 			 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set,
606 			 * see &enum iwl_rx_phy_data1.
607 			 */
608 			__le32 phy_data1;
609 		};
610 	};
611 	/* DW16 & DW17 */
612 	/**
613 	 * @reserved: reserved
614 	 */
615 	__le32 reserved[2];
616 } __packed; /* RX_MPDU_RES_START_API_S_VER_3 */
617 
618 /**
619  * struct iwl_rx_mpdu_desc - RX MPDU descriptor
620  */
621 struct iwl_rx_mpdu_desc {
622 	/* DW2 */
623 	/**
624 	 * @mpdu_len: MPDU length
625 	 */
626 	__le16 mpdu_len;
627 	/**
628 	 * @mac_flags1: &enum iwl_rx_mpdu_mac_flags1
629 	 */
630 	u8 mac_flags1;
631 	/**
632 	 * @mac_flags2: &enum iwl_rx_mpdu_mac_flags2
633 	 */
634 	u8 mac_flags2;
635 	/* DW3 */
636 	/**
637 	 * @amsdu_info: &enum iwl_rx_mpdu_amsdu_info
638 	 */
639 	u8 amsdu_info;
640 	/**
641 	 * @phy_info: &enum iwl_rx_mpdu_phy_info
642 	 */
643 	__le16 phy_info;
644 	/**
645 	 * @mac_phy_idx: MAC/PHY index
646 	 */
647 	u8 mac_phy_idx;
648 	/* DW4 - carries csum data only when rpa_en == 1 */
649 	/**
650 	 * @raw_csum: raw checksum (alledgedly unreliable)
651 	 */
652 	__le16 raw_csum;
653 
654 	union {
655 		/**
656 		 * @l3l4_flags: &enum iwl_rx_l3l4_flags
657 		 */
658 		__le16 l3l4_flags;
659 
660 		/**
661 		 * @phy_data4: depends on info type, see phy_data1
662 		 */
663 		__le16 phy_data4;
664 	};
665 	/* DW5 */
666 	/**
667 	 * @status: &enum iwl_rx_mpdu_status
668 	 */
669 	__le32 status;
670 
671 	/* DW6 */
672 	/**
673 	 * @reorder_data: &enum iwl_rx_mpdu_reorder_data
674 	 */
675 	__le32 reorder_data;
676 
677 	union {
678 		struct iwl_rx_mpdu_desc_v1 v1;
679 		struct iwl_rx_mpdu_desc_v3 v3;
680 	};
681 } __packed; /* RX_MPDU_RES_START_API_S_VER_3 */
682 
683 #define IWL_RX_DESC_SIZE_V1 offsetofend(struct iwl_rx_mpdu_desc, v1)
684 
685 #define RX_NO_DATA_CHAIN_A_POS		0
686 #define RX_NO_DATA_CHAIN_A_MSK		(0xff << RX_NO_DATA_CHAIN_A_POS)
687 #define RX_NO_DATA_CHAIN_B_POS		8
688 #define RX_NO_DATA_CHAIN_B_MSK		(0xff << RX_NO_DATA_CHAIN_B_POS)
689 #define RX_NO_DATA_CHANNEL_POS		16
690 #define RX_NO_DATA_CHANNEL_MSK		(0xff << RX_NO_DATA_CHANNEL_POS)
691 
692 #define RX_NO_DATA_INFO_TYPE_POS	0
693 #define RX_NO_DATA_INFO_TYPE_MSK	(0xff << RX_NO_DATA_INFO_TYPE_POS)
694 #define RX_NO_DATA_INFO_TYPE_NONE	0
695 #define RX_NO_DATA_INFO_TYPE_RX_ERR	1
696 #define RX_NO_DATA_INFO_TYPE_NDP	2
697 #define RX_NO_DATA_INFO_TYPE_MU_UNMATCHED	3
698 #define RX_NO_DATA_INFO_TYPE_HE_TB_UNMATCHED	4
699 
700 #define RX_NO_DATA_INFO_ERR_POS		8
701 #define RX_NO_DATA_INFO_ERR_MSK		(0xff << RX_NO_DATA_INFO_ERR_POS)
702 #define RX_NO_DATA_INFO_ERR_NONE	0
703 #define RX_NO_DATA_INFO_ERR_BAD_PLCP	1
704 #define RX_NO_DATA_INFO_ERR_UNSUPPORTED_RATE	2
705 #define RX_NO_DATA_INFO_ERR_NO_DELIM		3
706 #define RX_NO_DATA_INFO_ERR_BAD_MAC_HDR	4
707 
708 #define RX_NO_DATA_FRAME_TIME_POS	0
709 #define RX_NO_DATA_FRAME_TIME_MSK	(0xfffff << RX_NO_DATA_FRAME_TIME_POS)
710 
711 #define RX_NO_DATA_RX_VEC0_HE_NSTS_MSK	0x03800000
712 #define RX_NO_DATA_RX_VEC0_VHT_NSTS_MSK	0x38000000
713 
714 /**
715  * struct iwl_rx_no_data - RX no data descriptor
716  * @info: 7:0 frame type, 15:8 RX error type
717  * @rssi: 7:0 energy chain-A,
718  *	15:8 chain-B, measured at FINA time (FINA_ENERGY), 16:23 channel
719  * @on_air_rise_time: GP2 during on air rise
720  * @fr_time: frame time
721  * @rate: rate/mcs of frame
722  * @phy_info: &enum iwl_rx_phy_data0 and &enum iwl_rx_phy_info_type
723  * @rx_vec: DW-12:9 raw RX vectors from DSP according to modulation type.
724  *	for VHT: OFDM_RX_VECTOR_SIGA1_OUT, OFDM_RX_VECTOR_SIGA2_OUT
725  *	for HE: OFDM_RX_VECTOR_HE_SIGA1_OUT, OFDM_RX_VECTOR_HE_SIGA2_OUT
726  */
727 struct iwl_rx_no_data {
728 	__le32 info;
729 	__le32 rssi;
730 	__le32 on_air_rise_time;
731 	__le32 fr_time;
732 	__le32 rate;
733 	__le32 phy_info[2];
734 	__le32 rx_vec[2];
735 } __packed; /* RX_NO_DATA_NTFY_API_S_VER_1 */
736 
737 struct iwl_frame_release {
738 	u8 baid;
739 	u8 reserved;
740 	__le16 nssn;
741 };
742 
743 /**
744  * enum iwl_bar_frame_release_sta_tid - STA/TID information for BAR release
745  * @IWL_BAR_FRAME_RELEASE_TID_MASK: TID mask
746  * @IWL_BAR_FRAME_RELEASE_STA_MASK: STA mask
747  */
748 enum iwl_bar_frame_release_sta_tid {
749 	IWL_BAR_FRAME_RELEASE_TID_MASK = 0x0000000f,
750 	IWL_BAR_FRAME_RELEASE_STA_MASK = 0x000001f0,
751 };
752 
753 /**
754  * enum iwl_bar_frame_release_ba_info - BA information for BAR release
755  * @IWL_BAR_FRAME_RELEASE_NSSN_MASK: NSSN mask
756  * @IWL_BAR_FRAME_RELEASE_SN_MASK: SN mask (ignored by driver)
757  * @IWL_BAR_FRAME_RELEASE_BAID_MASK: BAID mask
758  */
759 enum iwl_bar_frame_release_ba_info {
760 	IWL_BAR_FRAME_RELEASE_NSSN_MASK	= 0x00000fff,
761 	IWL_BAR_FRAME_RELEASE_SN_MASK	= 0x00fff000,
762 	IWL_BAR_FRAME_RELEASE_BAID_MASK	= 0x3f000000,
763 };
764 
765 /**
766  * struct iwl_bar_frame_release - frame release from BAR info
767  * @sta_tid: STA & TID information, see &enum iwl_bar_frame_release_sta_tid.
768  * @ba_info: BA information, see &enum iwl_bar_frame_release_ba_info.
769  */
770 struct iwl_bar_frame_release {
771 	__le32 sta_tid;
772 	__le32 ba_info;
773 } __packed; /* RX_BAR_TO_FRAME_RELEASE_API_S_VER_1 */
774 
775 enum iwl_rss_hash_func_en {
776 	IWL_RSS_HASH_TYPE_IPV4_TCP,
777 	IWL_RSS_HASH_TYPE_IPV4_UDP,
778 	IWL_RSS_HASH_TYPE_IPV4_PAYLOAD,
779 	IWL_RSS_HASH_TYPE_IPV6_TCP,
780 	IWL_RSS_HASH_TYPE_IPV6_UDP,
781 	IWL_RSS_HASH_TYPE_IPV6_PAYLOAD,
782 };
783 
784 #define IWL_RSS_HASH_KEY_CNT 10
785 #define IWL_RSS_INDIRECTION_TABLE_SIZE 128
786 #define IWL_RSS_ENABLE 1
787 
788 /**
789  * struct iwl_rss_config_cmd - RSS (Receive Side Scaling) configuration
790  *
791  * @flags: 1 - enable, 0 - disable
792  * @hash_mask: Type of RSS to use. Values are from %iwl_rss_hash_func_en
793  * @reserved: reserved
794  * @secret_key: 320 bit input of random key configuration from driver
795  * @indirection_table: indirection table
796  */
797 struct iwl_rss_config_cmd {
798 	__le32 flags;
799 	u8 hash_mask;
800 	u8 reserved[3];
801 	__le32 secret_key[IWL_RSS_HASH_KEY_CNT];
802 	u8 indirection_table[IWL_RSS_INDIRECTION_TABLE_SIZE];
803 } __packed; /* RSS_CONFIG_CMD_API_S_VER_1 */
804 
805 #define IWL_MULTI_QUEUE_SYNC_SENDER_POS 0
806 #define IWL_MULTI_QUEUE_SYNC_SENDER_MSK 0xf
807 
808 /**
809  * struct iwl_rxq_sync_cmd - RXQ notification trigger
810  *
811  * @flags: flags of the notification. bit 0:3 are the sender queue
812  * @rxq_mask: rx queues to send the notification on
813  * @count: number of bytes in payload, should be DWORD aligned
814  * @payload: data to send to rx queues
815  */
816 struct iwl_rxq_sync_cmd {
817 	__le32 flags;
818 	__le32 rxq_mask;
819 	__le32 count;
820 	u8 payload[];
821 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */
822 
823 /**
824  * struct iwl_rxq_sync_notification - Notification triggered by RXQ
825  * sync command
826  *
827  * @count: number of bytes in payload
828  * @payload: data to send to rx queues
829  */
830 struct iwl_rxq_sync_notification {
831 	__le32 count;
832 	u8 payload[];
833 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */
834 
835 /**
836  * enum iwl_mvm_rxq_notif_type - Internal message identifier
837  *
838  * @IWL_MVM_RXQ_EMPTY: empty sync notification
839  * @IWL_MVM_RXQ_NOTIF_DEL_BA: notify RSS queues of delBA
840  * @IWL_MVM_RXQ_NSSN_SYNC: notify all the RSS queues with the new NSSN
841  */
842 enum iwl_mvm_rxq_notif_type {
843 	IWL_MVM_RXQ_EMPTY,
844 	IWL_MVM_RXQ_NOTIF_DEL_BA,
845 	IWL_MVM_RXQ_NSSN_SYNC,
846 };
847 
848 /**
849  * struct iwl_mvm_internal_rxq_notif - Internal representation of the data sent
850  * in &iwl_rxq_sync_cmd. Should be DWORD aligned.
851  * FW is agnostic to the payload, so there are no endianity requirements.
852  *
853  * @type: value from &iwl_mvm_rxq_notif_type
854  * @sync: ctrl path is waiting for all notifications to be received
855  * @cookie: internal cookie to identify old notifications
856  * @data: payload
857  */
858 struct iwl_mvm_internal_rxq_notif {
859 	u16 type;
860 	u16 sync;
861 	u32 cookie;
862 	u8 data[];
863 } __packed;
864 
865 /**
866  * enum iwl_mvm_pm_event - type of station PM event
867  * @IWL_MVM_PM_EVENT_AWAKE: station woke up
868  * @IWL_MVM_PM_EVENT_ASLEEP: station went to sleep
869  * @IWL_MVM_PM_EVENT_UAPSD: station sent uAPSD trigger
870  * @IWL_MVM_PM_EVENT_PS_POLL: station sent PS-Poll
871  */
872 enum iwl_mvm_pm_event {
873 	IWL_MVM_PM_EVENT_AWAKE,
874 	IWL_MVM_PM_EVENT_ASLEEP,
875 	IWL_MVM_PM_EVENT_UAPSD,
876 	IWL_MVM_PM_EVENT_PS_POLL,
877 }; /* PEER_PM_NTFY_API_E_VER_1 */
878 
879 /**
880  * struct iwl_mvm_pm_state_notification - station PM state notification
881  * @sta_id: station ID of the station changing state
882  * @type: the new powersave state, see &enum iwl_mvm_pm_event
883  */
884 struct iwl_mvm_pm_state_notification {
885 	u8 sta_id;
886 	u8 type;
887 	/* private: */
888 	__le16 reserved;
889 } __packed; /* PEER_PM_NTFY_API_S_VER_1 */
890 
891 #define BA_WINDOW_STREAMS_MAX		16
892 #define BA_WINDOW_STATUS_TID_MSK	0x000F
893 #define BA_WINDOW_STATUS_STA_ID_POS	4
894 #define BA_WINDOW_STATUS_STA_ID_MSK	0x01F0
895 #define BA_WINDOW_STATUS_VALID_MSK	BIT(9)
896 
897 /**
898  * struct iwl_ba_window_status_notif - reordering window's status notification
899  * @bitmap: bitmap of received frames [start_seq_num + 0]..[start_seq_num + 63]
900  * @ra_tid: bit 3:0 - TID, bit 8:4 - STA_ID, bit 9 - valid
901  * @start_seq_num: the start sequence number of the bitmap
902  * @mpdu_rx_count: the number of received MPDUs since entering D0i3
903  */
904 struct iwl_ba_window_status_notif {
905 	__le64 bitmap[BA_WINDOW_STREAMS_MAX];
906 	__le16 ra_tid[BA_WINDOW_STREAMS_MAX];
907 	__le32 start_seq_num[BA_WINDOW_STREAMS_MAX];
908 	__le16 mpdu_rx_count[BA_WINDOW_STREAMS_MAX];
909 } __packed; /* BA_WINDOW_STATUS_NTFY_API_S_VER_1 */
910 
911 /**
912  * struct iwl_rfh_queue_config - RX queue configuration
913  * @q_num: Q num
914  * @enable: enable queue
915  * @reserved: alignment
916  * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr
917  * @fr_bd_cb: DMA address of freeRB table
918  * @ur_bd_cb: DMA address of used RB table
919  * @fr_bd_wid: Initial index of the free table
920  */
921 struct iwl_rfh_queue_data {
922 	u8 q_num;
923 	u8 enable;
924 	__le16 reserved;
925 	__le64 urbd_stts_wrptr;
926 	__le64 fr_bd_cb;
927 	__le64 ur_bd_cb;
928 	__le32 fr_bd_wid;
929 } __packed; /* RFH_QUEUE_CONFIG_S_VER_1 */
930 
931 /**
932  * struct iwl_rfh_queue_config - RX queue configuration
933  * @num_queues: number of queues configured
934  * @reserved: alignment
935  * @data: DMA addresses per-queue
936  */
937 struct iwl_rfh_queue_config {
938 	u8 num_queues;
939 	u8 reserved[3];
940 	struct iwl_rfh_queue_data data[];
941 } __packed; /* RFH_QUEUE_CONFIG_API_S_VER_1 */
942 
943 #endif /* __iwl_fw_api_rx_h__ */
944