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Searched refs:SCL_COEF_RAM_SELECT (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dce/
Ddce_transform.h84 SRI(SCL_COEF_RAM_SELECT, SCL, id), \
154 SRI(SCL_COEF_RAM_SELECT, SCL, id), \
230 XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_FILTER_TYPE, mask_sh), \
231 XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_PHASE, mask_sh), \
232 XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_TAP_PAIR_IDX, mask_sh), \
321 XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_FILTER_TYPE, mask_sh), \
322 XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_PHASE, mask_sh), \
323 XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_TAP_PAIR_IDX, mask_sh), \
585 uint32_t SCL_COEF_RAM_SELECT; member
Ddce_transform.c237 REG_SET_3(SCL_COEF_RAM_SELECT, 0, in program_multi_taps_filter()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_dpp_dscl.c387 SCL_COEF_RAM_SELECT, !coef_ram_current, in dpp1_dscl_set_scl_filter()
Ddcn10_dpp.h229 TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT, mask_sh),\
513 type SCL_COEF_RAM_SELECT; \
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dpp.h255 TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT, mask_sh),\