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Searched refs:SDMA0_BASE__INST3_SEG5 (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/amd/include/
Dvega20_ip_offset.h698 #define SDMA0_BASE__INST3_SEG5 0 macro
Darct_ip_offset.h944 #define SDMA0_BASE__INST3_SEG5 0 macro