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Searched refs:SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/sdma1/
Dsdma1_4_0_sh_mask.h1451 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L macro
Dsdma1_4_2_sh_mask.h1457 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK … macro
Dsdma1_4_2_2_sh_mask.h1465 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK … macro
/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_sh_mask.h1847 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 macro
Doss_2_0_sh_mask.h1647 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 macro
Doss_3_0_1_sh_mask.h2793 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 macro
Doss_3_0_sh_mask.h2907 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_3_0_sh_mask.h4183 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK … macro
Dgc_10_1_0_sh_mask.h4014 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK … macro