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Searched refs:SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/sdma1/
Dsdma1_4_0_sh_mask.h1660 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 macro
Dsdma1_4_2_sh_mask.h1668 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT … macro
Dsdma1_4_2_2_sh_mask.h1676 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT … macro
/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_sh_mask.h1978 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 macro
Doss_2_0_sh_mask.h1762 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 macro
Doss_3_0_1_sh_mask.h2952 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 macro
Doss_3_0_sh_mask.h3060 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_3_0_sh_mask.h4407 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT … macro
Dgc_10_1_0_sh_mask.h4228 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT … macro