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Searched refs:SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/sdma1/
Dsdma1_4_2_sh_mask.h2487 #define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT … macro
Dsdma1_4_2_2_sh_mask.h2495 #define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT … macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_3_0_sh_mask.h5272 #define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT … macro
Dgc_10_1_0_sh_mask.h5053 #define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT … macro