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Searched refs:SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/sdma1/
Dsdma1_4_0_sh_mask.h505 #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c macro
Dsdma1_4_2_sh_mask.h503 #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT … macro
Dsdma1_4_2_2_sh_mask.h507 #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT … macro
/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_sh_mask.h1640 #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c macro
Doss_2_0_sh_mask.h1476 #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c macro
Doss_3_0_1_sh_mask.h2158 #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c macro
Doss_3_0_sh_mask.h2462 #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_3_0_sh_mask.h3092 #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT … macro
Dgc_10_1_0_sh_mask.h2985 #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT … macro