1 /* 2 * Copyright (C) 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 */ 22 23 #ifndef __NAVI10_SDMA_PKT_OPEN_H_ 24 #define __NAVI10_SDMA_PKT_OPEN_H_ 25 26 #define SDMA_OP_NOP 0 27 #define SDMA_OP_COPY 1 28 #define SDMA_OP_WRITE 2 29 #define SDMA_OP_INDIRECT 4 30 #define SDMA_OP_FENCE 5 31 #define SDMA_OP_TRAP 6 32 #define SDMA_OP_SEM 7 33 #define SDMA_OP_POLL_REGMEM 8 34 #define SDMA_OP_COND_EXE 9 35 #define SDMA_OP_ATOMIC 10 36 #define SDMA_OP_CONST_FILL 11 37 #define SDMA_OP_PTEPDE 12 38 #define SDMA_OP_TIMESTAMP 13 39 #define SDMA_OP_SRBM_WRITE 14 40 #define SDMA_OP_PRE_EXE 15 41 #define SDMA_OP_GPUVM_INV 16 42 #define SDMA_OP_GCR_REQ 17 43 #define SDMA_OP_DUMMY_TRAP 32 44 #define SDMA_SUBOP_TIMESTAMP_SET 0 45 #define SDMA_SUBOP_TIMESTAMP_GET 1 46 #define SDMA_SUBOP_TIMESTAMP_GET_GLOBAL 2 47 #define SDMA_SUBOP_COPY_LINEAR 0 48 #define SDMA_SUBOP_COPY_LINEAR_SUB_WIND 4 49 #define SDMA_SUBOP_COPY_TILED 1 50 #define SDMA_SUBOP_COPY_TILED_SUB_WIND 5 51 #define SDMA_SUBOP_COPY_T2T_SUB_WIND 6 52 #define SDMA_SUBOP_COPY_SOA 3 53 #define SDMA_SUBOP_COPY_DIRTY_PAGE 7 54 #define SDMA_SUBOP_COPY_LINEAR_PHY 8 55 #define SDMA_SUBOP_COPY_LINEAR_BC 16 56 #define SDMA_SUBOP_COPY_TILED_BC 17 57 #define SDMA_SUBOP_COPY_LINEAR_SUB_WIND_BC 20 58 #define SDMA_SUBOP_COPY_TILED_SUB_WIND_BC 21 59 #define SDMA_SUBOP_COPY_T2T_SUB_WIND_BC 22 60 #define SDMA_SUBOP_WRITE_LINEAR 0 61 #define SDMA_SUBOP_WRITE_TILED 1 62 #define SDMA_SUBOP_WRITE_TILED_BC 17 63 #define SDMA_SUBOP_PTEPDE_GEN 0 64 #define SDMA_SUBOP_PTEPDE_COPY 1 65 #define SDMA_SUBOP_PTEPDE_RMW 2 66 #define SDMA_SUBOP_PTEPDE_COPY_BACKWARDS 3 67 #define SDMA_SUBOP_DATA_FILL_MULTI 1 68 #define SDMA_SUBOP_POLL_REG_WRITE_MEM 1 69 #define SDMA_SUBOP_POLL_DBIT_WRITE_MEM 2 70 #define SDMA_SUBOP_POLL_MEM_VERIFY 3 71 #define HEADER_AGENT_DISPATCH 4 72 #define HEADER_BARRIER 5 73 #define SDMA_OP_AQL_COPY 0 74 #define SDMA_OP_AQL_BARRIER_OR 0 75 76 #define SDMA_GCR_RANGE_IS_PA (1 << 18) 77 #define SDMA_GCR_SEQ(x) (((x) & 0x3) << 16) 78 #define SDMA_GCR_GL2_WB (1 << 15) 79 #define SDMA_GCR_GL2_INV (1 << 14) 80 #define SDMA_GCR_GL2_DISCARD (1 << 13) 81 #define SDMA_GCR_GL2_RANGE(x) (((x) & 0x3) << 11) 82 #define SDMA_GCR_GL2_US (1 << 10) 83 #define SDMA_GCR_GL1_INV (1 << 9) 84 #define SDMA_GCR_GLV_INV (1 << 8) 85 #define SDMA_GCR_GLK_INV (1 << 7) 86 #define SDMA_GCR_GLK_WB (1 << 6) 87 #define SDMA_GCR_GLM_INV (1 << 5) 88 #define SDMA_GCR_GLM_WB (1 << 4) 89 #define SDMA_GCR_GL1_RANGE(x) (((x) & 0x3) << 2) 90 #define SDMA_GCR_GLI_INV(x) (((x) & 0x3) << 0) 91 92 /*define for op field*/ 93 #define SDMA_PKT_HEADER_op_offset 0 94 #define SDMA_PKT_HEADER_op_mask 0x000000FF 95 #define SDMA_PKT_HEADER_op_shift 0 96 #define SDMA_PKT_HEADER_OP(x) (((x) & SDMA_PKT_HEADER_op_mask) << SDMA_PKT_HEADER_op_shift) 97 98 /*define for sub_op field*/ 99 #define SDMA_PKT_HEADER_sub_op_offset 0 100 #define SDMA_PKT_HEADER_sub_op_mask 0x000000FF 101 #define SDMA_PKT_HEADER_sub_op_shift 8 102 #define SDMA_PKT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_HEADER_sub_op_mask) << SDMA_PKT_HEADER_sub_op_shift) 103 104 /* 105 ** Definitions for SDMA_PKT_COPY_LINEAR packet 106 */ 107 108 /*define for HEADER word*/ 109 /*define for op field*/ 110 #define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0 111 #define SDMA_PKT_COPY_LINEAR_HEADER_op_mask 0x000000FF 112 #define SDMA_PKT_COPY_LINEAR_HEADER_op_shift 0 113 #define SDMA_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_op_shift) 114 115 /*define for sub_op field*/ 116 #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset 0 117 #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask 0x000000FF 118 #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift 8 119 #define SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift) 120 121 /*define for encrypt field*/ 122 #define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset 0 123 #define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask 0x00000001 124 #define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift 16 125 #define SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift) 126 127 /*define for tmz field*/ 128 #define SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset 0 129 #define SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask 0x00000001 130 #define SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift 18 131 #define SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift) 132 133 /*define for backwards field*/ 134 #define SDMA_PKT_COPY_LINEAR_HEADER_backwards_offset 0 135 #define SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask 0x00000001 136 #define SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift 25 137 #define SDMA_PKT_COPY_LINEAR_HEADER_BACKWARDS(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask) << SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift) 138 139 /*define for broadcast field*/ 140 #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset 0 141 #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask 0x00000001 142 #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift 27 143 #define SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift) 144 145 /*define for COUNT word*/ 146 /*define for count field*/ 147 #define SDMA_PKT_COPY_LINEAR_COUNT_count_offset 1 148 #define SDMA_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF 149 #define SDMA_PKT_COPY_LINEAR_COUNT_count_shift 0 150 #define SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_COUNT_count_shift) 151 152 /*define for PARAMETER word*/ 153 /*define for dst_sw field*/ 154 #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 2 155 #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003 156 #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16 157 #define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) 158 159 /*define for src_sw field*/ 160 #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 2 161 #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003 162 #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24 163 #define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) 164 165 /*define for SRC_ADDR_LO word*/ 166 /*define for src_addr_31_0 field*/ 167 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 168 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 169 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 170 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 171 172 /*define for SRC_ADDR_HI word*/ 173 /*define for src_addr_63_32 field*/ 174 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 175 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 176 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 177 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 178 179 /*define for DST_ADDR_LO word*/ 180 /*define for dst_addr_31_0 field*/ 181 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5 182 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 183 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 184 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) 185 186 /*define for DST_ADDR_HI word*/ 187 /*define for dst_addr_63_32 field*/ 188 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6 189 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 190 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 191 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) 192 193 194 /* 195 ** Definitions for SDMA_PKT_COPY_LINEAR_BC packet 196 */ 197 198 /*define for HEADER word*/ 199 /*define for op field*/ 200 #define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_offset 0 201 #define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask 0x000000FF 202 #define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift 0 203 #define SDMA_PKT_COPY_LINEAR_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift) 204 205 /*define for sub_op field*/ 206 #define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_offset 0 207 #define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask 0x000000FF 208 #define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift 8 209 #define SDMA_PKT_COPY_LINEAR_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift) 210 211 /*define for COUNT word*/ 212 /*define for count field*/ 213 #define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_offset 1 214 #define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask 0x003FFFFF 215 #define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift 0 216 #define SDMA_PKT_COPY_LINEAR_BC_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift) 217 218 /*define for PARAMETER word*/ 219 /*define for dst_sw field*/ 220 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_offset 2 221 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask 0x00000003 222 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift 16 223 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift) 224 225 /*define for dst_ha field*/ 226 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_offset 2 227 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask 0x00000001 228 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift 22 229 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift) 230 231 /*define for src_sw field*/ 232 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_offset 2 233 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask 0x00000003 234 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift 24 235 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift) 236 237 /*define for src_ha field*/ 238 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_offset 2 239 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask 0x00000001 240 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift 30 241 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift) 242 243 /*define for SRC_ADDR_LO word*/ 244 /*define for src_addr_31_0 field*/ 245 #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_offset 3 246 #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 247 #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift 0 248 #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift) 249 250 /*define for SRC_ADDR_HI word*/ 251 /*define for src_addr_63_32 field*/ 252 #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_offset 4 253 #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 254 #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift 0 255 #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift) 256 257 /*define for DST_ADDR_LO word*/ 258 /*define for dst_addr_31_0 field*/ 259 #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_offset 5 260 #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 261 #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 262 #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift) 263 264 /*define for DST_ADDR_HI word*/ 265 /*define for dst_addr_63_32 field*/ 266 #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_offset 6 267 #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 268 #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 269 #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift) 270 271 272 /* 273 ** Definitions for SDMA_PKT_COPY_DIRTY_PAGE packet 274 */ 275 276 /*define for HEADER word*/ 277 /*define for op field*/ 278 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset 0 279 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask 0x000000FF 280 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift 0 281 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift) 282 283 /*define for sub_op field*/ 284 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset 0 285 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask 0x000000FF 286 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift 8 287 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift) 288 289 /*define for tmz field*/ 290 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset 0 291 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask 0x00000001 292 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift 18 293 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift) 294 295 /*define for all field*/ 296 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset 0 297 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask 0x00000001 298 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift 31 299 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift) 300 301 /*define for COUNT word*/ 302 /*define for count field*/ 303 #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset 1 304 #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask 0x003FFFFF 305 #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift 0 306 #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask) << SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift) 307 308 /*define for PARAMETER word*/ 309 /*define for dst_mtype field*/ 310 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_offset 2 311 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask 0x00000007 312 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift 3 313 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_MTYPE(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift) 314 315 /*define for dst_l2_policy field*/ 316 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_offset 2 317 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask 0x00000003 318 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift 6 319 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_L2_POLICY(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift) 320 321 /*define for src_mtype field*/ 322 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_offset 2 323 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask 0x00000007 324 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift 11 325 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_MTYPE(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift) 326 327 /*define for src_l2_policy field*/ 328 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_offset 2 329 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask 0x00000003 330 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift 14 331 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_L2_POLICY(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift) 332 333 /*define for dst_sw field*/ 334 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset 2 335 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask 0x00000003 336 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift 16 337 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift) 338 339 /*define for dst_gcc field*/ 340 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset 2 341 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask 0x00000001 342 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift 19 343 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift) 344 345 /*define for dst_sys field*/ 346 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset 2 347 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask 0x00000001 348 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift 20 349 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift) 350 351 /*define for dst_snoop field*/ 352 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset 2 353 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask 0x00000001 354 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift 22 355 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift) 356 357 /*define for dst_gpa field*/ 358 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset 2 359 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask 0x00000001 360 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift 23 361 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift) 362 363 /*define for src_sw field*/ 364 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset 2 365 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask 0x00000003 366 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift 24 367 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift) 368 369 /*define for src_sys field*/ 370 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset 2 371 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask 0x00000001 372 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift 28 373 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift) 374 375 /*define for src_snoop field*/ 376 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset 2 377 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask 0x00000001 378 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift 30 379 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift) 380 381 /*define for src_gpa field*/ 382 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset 2 383 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask 0x00000001 384 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift 31 385 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift) 386 387 /*define for SRC_ADDR_LO word*/ 388 /*define for src_addr_31_0 field*/ 389 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset 3 390 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 391 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift 0 392 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift) 393 394 /*define for SRC_ADDR_HI word*/ 395 /*define for src_addr_63_32 field*/ 396 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset 4 397 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 398 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift 0 399 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift) 400 401 /*define for DST_ADDR_LO word*/ 402 /*define for dst_addr_31_0 field*/ 403 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset 5 404 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 405 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift 0 406 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift) 407 408 /*define for DST_ADDR_HI word*/ 409 /*define for dst_addr_63_32 field*/ 410 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset 6 411 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 412 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift 0 413 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift) 414 415 416 /* 417 ** Definitions for SDMA_PKT_COPY_PHYSICAL_LINEAR packet 418 */ 419 420 /*define for HEADER word*/ 421 /*define for op field*/ 422 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset 0 423 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask 0x000000FF 424 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift 0 425 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift) 426 427 /*define for sub_op field*/ 428 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset 0 429 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask 0x000000FF 430 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift 8 431 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift) 432 433 /*define for tmz field*/ 434 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset 0 435 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask 0x00000001 436 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift 18 437 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift) 438 439 /*define for COUNT word*/ 440 /*define for count field*/ 441 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset 1 442 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask 0x003FFFFF 443 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift 0 444 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift) 445 446 /*define for PARAMETER word*/ 447 /*define for dst_mtype field*/ 448 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_offset 2 449 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask 0x00000007 450 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift 3 451 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_MTYPE(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift) 452 453 /*define for dst_l2_policy field*/ 454 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_offset 2 455 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask 0x00000003 456 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift 6 457 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_L2_POLICY(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift) 458 459 /*define for src_mtype field*/ 460 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_offset 2 461 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask 0x00000007 462 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift 11 463 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_MTYPE(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift) 464 465 /*define for src_l2_policy field*/ 466 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_offset 2 467 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask 0x00000003 468 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift 14 469 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_L2_POLICY(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift) 470 471 /*define for dst_sw field*/ 472 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset 2 473 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask 0x00000003 474 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift 16 475 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift) 476 477 /*define for dst_gcc field*/ 478 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset 2 479 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask 0x00000001 480 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift 19 481 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift) 482 483 /*define for dst_sys field*/ 484 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset 2 485 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask 0x00000001 486 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift 20 487 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift) 488 489 /*define for dst_log field*/ 490 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset 2 491 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask 0x00000001 492 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift 21 493 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift) 494 495 /*define for dst_snoop field*/ 496 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset 2 497 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask 0x00000001 498 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift 22 499 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift) 500 501 /*define for dst_gpa field*/ 502 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset 2 503 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask 0x00000001 504 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift 23 505 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift) 506 507 /*define for src_sw field*/ 508 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset 2 509 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask 0x00000003 510 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift 24 511 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift) 512 513 /*define for src_gcc field*/ 514 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset 2 515 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask 0x00000001 516 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift 27 517 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift) 518 519 /*define for src_sys field*/ 520 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset 2 521 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask 0x00000001 522 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift 28 523 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift) 524 525 /*define for src_snoop field*/ 526 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset 2 527 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask 0x00000001 528 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift 30 529 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift) 530 531 /*define for src_gpa field*/ 532 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset 2 533 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask 0x00000001 534 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift 31 535 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift) 536 537 /*define for SRC_ADDR_LO word*/ 538 /*define for src_addr_31_0 field*/ 539 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 540 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 541 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 542 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 543 544 /*define for SRC_ADDR_HI word*/ 545 /*define for src_addr_63_32 field*/ 546 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 547 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 548 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 549 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 550 551 /*define for DST_ADDR_LO word*/ 552 /*define for dst_addr_31_0 field*/ 553 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5 554 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 555 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 556 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) 557 558 /*define for DST_ADDR_HI word*/ 559 /*define for dst_addr_63_32 field*/ 560 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6 561 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 562 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 563 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) 564 565 566 /* 567 ** Definitions for SDMA_PKT_COPY_BROADCAST_LINEAR packet 568 */ 569 570 /*define for HEADER word*/ 571 /*define for op field*/ 572 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset 0 573 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask 0x000000FF 574 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift 0 575 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift) 576 577 /*define for sub_op field*/ 578 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset 0 579 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask 0x000000FF 580 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift 8 581 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift) 582 583 /*define for encrypt field*/ 584 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset 0 585 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask 0x00000001 586 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift 16 587 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift) 588 589 /*define for tmz field*/ 590 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset 0 591 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask 0x00000001 592 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift 18 593 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift) 594 595 /*define for broadcast field*/ 596 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset 0 597 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask 0x00000001 598 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift 27 599 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift) 600 601 /*define for COUNT word*/ 602 /*define for count field*/ 603 #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset 1 604 #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask 0x003FFFFF 605 #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift 0 606 #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift) 607 608 /*define for PARAMETER word*/ 609 /*define for dst2_sw field*/ 610 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset 2 611 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask 0x00000003 612 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift 8 613 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift) 614 615 /*define for dst1_sw field*/ 616 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset 2 617 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask 0x00000003 618 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift 16 619 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift) 620 621 /*define for src_sw field*/ 622 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset 2 623 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask 0x00000003 624 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift 24 625 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift) 626 627 /*define for SRC_ADDR_LO word*/ 628 /*define for src_addr_31_0 field*/ 629 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 630 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 631 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 632 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 633 634 /*define for SRC_ADDR_HI word*/ 635 /*define for src_addr_63_32 field*/ 636 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 637 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 638 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 639 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 640 641 /*define for DST1_ADDR_LO word*/ 642 /*define for dst1_addr_31_0 field*/ 643 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset 5 644 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask 0xFFFFFFFF 645 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift 0 646 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift) 647 648 /*define for DST1_ADDR_HI word*/ 649 /*define for dst1_addr_63_32 field*/ 650 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset 6 651 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask 0xFFFFFFFF 652 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift 0 653 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift) 654 655 /*define for DST2_ADDR_LO word*/ 656 /*define for dst2_addr_31_0 field*/ 657 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset 7 658 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask 0xFFFFFFFF 659 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift 0 660 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift) 661 662 /*define for DST2_ADDR_HI word*/ 663 /*define for dst2_addr_63_32 field*/ 664 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset 8 665 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask 0xFFFFFFFF 666 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift 0 667 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift) 668 669 670 /* 671 ** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN packet 672 */ 673 674 /*define for HEADER word*/ 675 /*define for op field*/ 676 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset 0 677 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask 0x000000FF 678 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift 0 679 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift) 680 681 /*define for sub_op field*/ 682 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset 0 683 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask 0x000000FF 684 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift 8 685 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift) 686 687 /*define for tmz field*/ 688 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset 0 689 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask 0x00000001 690 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift 18 691 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift) 692 693 /*define for elementsize field*/ 694 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset 0 695 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask 0x00000007 696 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift 29 697 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift) 698 699 /*define for SRC_ADDR_LO word*/ 700 /*define for src_addr_31_0 field*/ 701 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset 1 702 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 703 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift 0 704 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift) 705 706 /*define for SRC_ADDR_HI word*/ 707 /*define for src_addr_63_32 field*/ 708 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset 2 709 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 710 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift 0 711 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift) 712 713 /*define for DW_3 word*/ 714 /*define for src_x field*/ 715 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset 3 716 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask 0x00003FFF 717 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift 0 718 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift) 719 720 /*define for src_y field*/ 721 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset 3 722 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask 0x00003FFF 723 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift 16 724 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift) 725 726 /*define for DW_4 word*/ 727 /*define for src_z field*/ 728 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset 4 729 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask 0x00001FFF 730 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift 0 731 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift) 732 733 /*define for src_pitch field*/ 734 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset 4 735 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask 0x0007FFFF 736 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift 13 737 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift) 738 739 /*define for DW_5 word*/ 740 /*define for src_slice_pitch field*/ 741 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset 5 742 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask 0x0FFFFFFF 743 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift 0 744 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift) 745 746 /*define for DST_ADDR_LO word*/ 747 /*define for dst_addr_31_0 field*/ 748 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset 6 749 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 750 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift 0 751 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift) 752 753 /*define for DST_ADDR_HI word*/ 754 /*define for dst_addr_63_32 field*/ 755 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset 7 756 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 757 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift 0 758 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift) 759 760 /*define for DW_8 word*/ 761 /*define for dst_x field*/ 762 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset 8 763 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask 0x00003FFF 764 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift 0 765 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift) 766 767 /*define for dst_y field*/ 768 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset 8 769 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask 0x00003FFF 770 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift 16 771 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift) 772 773 /*define for DW_9 word*/ 774 /*define for dst_z field*/ 775 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset 9 776 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask 0x00001FFF 777 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift 0 778 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift) 779 780 /*define for dst_pitch field*/ 781 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset 9 782 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask 0x0007FFFF 783 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift 13 784 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift) 785 786 /*define for DW_10 word*/ 787 /*define for dst_slice_pitch field*/ 788 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset 10 789 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask 0x0FFFFFFF 790 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift 0 791 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift) 792 793 /*define for DW_11 word*/ 794 /*define for rect_x field*/ 795 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset 11 796 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask 0x00003FFF 797 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift 0 798 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift) 799 800 /*define for rect_y field*/ 801 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset 11 802 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask 0x00003FFF 803 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift 16 804 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift) 805 806 /*define for DW_12 word*/ 807 /*define for rect_z field*/ 808 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset 12 809 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask 0x00001FFF 810 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift 0 811 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift) 812 813 /*define for dst_sw field*/ 814 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset 12 815 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask 0x00000003 816 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift 16 817 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift) 818 819 /*define for src_sw field*/ 820 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset 12 821 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask 0x00000003 822 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift 24 823 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift) 824 825 826 /* 827 ** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN_BC packet 828 */ 829 830 /*define for HEADER word*/ 831 /*define for op field*/ 832 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_offset 0 833 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask 0x000000FF 834 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift 0 835 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift) 836 837 /*define for sub_op field*/ 838 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_offset 0 839 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask 0x000000FF 840 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift 8 841 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift) 842 843 /*define for elementsize field*/ 844 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_offset 0 845 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask 0x00000007 846 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift 29 847 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift) 848 849 /*define for SRC_ADDR_LO word*/ 850 /*define for src_addr_31_0 field*/ 851 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_offset 1 852 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 853 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift 0 854 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift) 855 856 /*define for SRC_ADDR_HI word*/ 857 /*define for src_addr_63_32 field*/ 858 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_offset 2 859 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 860 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift 0 861 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift) 862 863 /*define for DW_3 word*/ 864 /*define for src_x field*/ 865 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_offset 3 866 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask 0x00003FFF 867 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift 0 868 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift) 869 870 /*define for src_y field*/ 871 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_offset 3 872 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask 0x00003FFF 873 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift 16 874 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift) 875 876 /*define for DW_4 word*/ 877 /*define for src_z field*/ 878 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_offset 4 879 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask 0x000007FF 880 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift 0 881 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift) 882 883 /*define for src_pitch field*/ 884 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_offset 4 885 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask 0x00003FFF 886 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift 13 887 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift) 888 889 /*define for DW_5 word*/ 890 /*define for src_slice_pitch field*/ 891 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_offset 5 892 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask 0x0FFFFFFF 893 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift 0 894 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift) 895 896 /*define for DST_ADDR_LO word*/ 897 /*define for dst_addr_31_0 field*/ 898 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_offset 6 899 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 900 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 901 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift) 902 903 /*define for DST_ADDR_HI word*/ 904 /*define for dst_addr_63_32 field*/ 905 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_offset 7 906 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 907 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 908 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift) 909 910 /*define for DW_8 word*/ 911 /*define for dst_x field*/ 912 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_offset 8 913 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask 0x00003FFF 914 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift 0 915 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift) 916 917 /*define for dst_y field*/ 918 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_offset 8 919 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask 0x00003FFF 920 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift 16 921 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift) 922 923 /*define for DW_9 word*/ 924 /*define for dst_z field*/ 925 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_offset 9 926 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask 0x000007FF 927 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift 0 928 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift) 929 930 /*define for dst_pitch field*/ 931 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_offset 9 932 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask 0x00003FFF 933 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift 13 934 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift) 935 936 /*define for DW_10 word*/ 937 /*define for dst_slice_pitch field*/ 938 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_offset 10 939 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask 0x0FFFFFFF 940 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift 0 941 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift) 942 943 /*define for DW_11 word*/ 944 /*define for rect_x field*/ 945 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_offset 11 946 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask 0x00003FFF 947 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift 0 948 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift) 949 950 /*define for rect_y field*/ 951 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_offset 11 952 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask 0x00003FFF 953 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift 16 954 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift) 955 956 /*define for DW_12 word*/ 957 /*define for rect_z field*/ 958 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_offset 12 959 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask 0x000007FF 960 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift 0 961 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift) 962 963 /*define for dst_sw field*/ 964 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_offset 12 965 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask 0x00000003 966 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift 16 967 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift) 968 969 /*define for dst_ha field*/ 970 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_offset 12 971 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask 0x00000001 972 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift 22 973 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift) 974 975 /*define for src_sw field*/ 976 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_offset 12 977 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask 0x00000003 978 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift 24 979 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift) 980 981 /*define for src_ha field*/ 982 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_offset 12 983 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask 0x00000001 984 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift 30 985 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift) 986 987 988 /* 989 ** Definitions for SDMA_PKT_COPY_TILED packet 990 */ 991 992 /*define for HEADER word*/ 993 /*define for op field*/ 994 #define SDMA_PKT_COPY_TILED_HEADER_op_offset 0 995 #define SDMA_PKT_COPY_TILED_HEADER_op_mask 0x000000FF 996 #define SDMA_PKT_COPY_TILED_HEADER_op_shift 0 997 #define SDMA_PKT_COPY_TILED_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_op_mask) << SDMA_PKT_COPY_TILED_HEADER_op_shift) 998 999 /*define for sub_op field*/ 1000 #define SDMA_PKT_COPY_TILED_HEADER_sub_op_offset 0 1001 #define SDMA_PKT_COPY_TILED_HEADER_sub_op_mask 0x000000FF 1002 #define SDMA_PKT_COPY_TILED_HEADER_sub_op_shift 8 1003 #define SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_HEADER_sub_op_shift) 1004 1005 /*define for encrypt field*/ 1006 #define SDMA_PKT_COPY_TILED_HEADER_encrypt_offset 0 1007 #define SDMA_PKT_COPY_TILED_HEADER_encrypt_mask 0x00000001 1008 #define SDMA_PKT_COPY_TILED_HEADER_encrypt_shift 16 1009 #define SDMA_PKT_COPY_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_encrypt_mask) << SDMA_PKT_COPY_TILED_HEADER_encrypt_shift) 1010 1011 /*define for tmz field*/ 1012 #define SDMA_PKT_COPY_TILED_HEADER_tmz_offset 0 1013 #define SDMA_PKT_COPY_TILED_HEADER_tmz_mask 0x00000001 1014 #define SDMA_PKT_COPY_TILED_HEADER_tmz_shift 18 1015 #define SDMA_PKT_COPY_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_HEADER_tmz_shift) 1016 1017 /*define for detile field*/ 1018 #define SDMA_PKT_COPY_TILED_HEADER_detile_offset 0 1019 #define SDMA_PKT_COPY_TILED_HEADER_detile_mask 0x00000001 1020 #define SDMA_PKT_COPY_TILED_HEADER_detile_shift 31 1021 #define SDMA_PKT_COPY_TILED_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_HEADER_detile_shift) 1022 1023 /*define for TILED_ADDR_LO word*/ 1024 /*define for tiled_addr_31_0 field*/ 1025 #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset 1 1026 #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF 1027 #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift 0 1028 #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift) 1029 1030 /*define for TILED_ADDR_HI word*/ 1031 /*define for tiled_addr_63_32 field*/ 1032 #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset 2 1033 #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF 1034 #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift 0 1035 #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift) 1036 1037 /*define for DW_3 word*/ 1038 /*define for width field*/ 1039 #define SDMA_PKT_COPY_TILED_DW_3_width_offset 3 1040 #define SDMA_PKT_COPY_TILED_DW_3_width_mask 0x00003FFF 1041 #define SDMA_PKT_COPY_TILED_DW_3_width_shift 0 1042 #define SDMA_PKT_COPY_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_3_width_mask) << SDMA_PKT_COPY_TILED_DW_3_width_shift) 1043 1044 /*define for DW_4 word*/ 1045 /*define for height field*/ 1046 #define SDMA_PKT_COPY_TILED_DW_4_height_offset 4 1047 #define SDMA_PKT_COPY_TILED_DW_4_height_mask 0x00003FFF 1048 #define SDMA_PKT_COPY_TILED_DW_4_height_shift 0 1049 #define SDMA_PKT_COPY_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_height_mask) << SDMA_PKT_COPY_TILED_DW_4_height_shift) 1050 1051 /*define for depth field*/ 1052 #define SDMA_PKT_COPY_TILED_DW_4_depth_offset 4 1053 #define SDMA_PKT_COPY_TILED_DW_4_depth_mask 0x00001FFF 1054 #define SDMA_PKT_COPY_TILED_DW_4_depth_shift 16 1055 #define SDMA_PKT_COPY_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_DW_4_depth_shift) 1056 1057 /*define for DW_5 word*/ 1058 /*define for element_size field*/ 1059 #define SDMA_PKT_COPY_TILED_DW_5_element_size_offset 5 1060 #define SDMA_PKT_COPY_TILED_DW_5_element_size_mask 0x00000007 1061 #define SDMA_PKT_COPY_TILED_DW_5_element_size_shift 0 1062 #define SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_DW_5_element_size_shift) 1063 1064 /*define for swizzle_mode field*/ 1065 #define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset 5 1066 #define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask 0x0000001F 1067 #define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift 3 1068 #define SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift) 1069 1070 /*define for dimension field*/ 1071 #define SDMA_PKT_COPY_TILED_DW_5_dimension_offset 5 1072 #define SDMA_PKT_COPY_TILED_DW_5_dimension_mask 0x00000003 1073 #define SDMA_PKT_COPY_TILED_DW_5_dimension_shift 9 1074 #define SDMA_PKT_COPY_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_dimension_mask) << SDMA_PKT_COPY_TILED_DW_5_dimension_shift) 1075 1076 /*define for mip_max field*/ 1077 #define SDMA_PKT_COPY_TILED_DW_5_mip_max_offset 5 1078 #define SDMA_PKT_COPY_TILED_DW_5_mip_max_mask 0x0000000F 1079 #define SDMA_PKT_COPY_TILED_DW_5_mip_max_shift 16 1080 #define SDMA_PKT_COPY_TILED_DW_5_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_mip_max_mask) << SDMA_PKT_COPY_TILED_DW_5_mip_max_shift) 1081 1082 /*define for DW_6 word*/ 1083 /*define for x field*/ 1084 #define SDMA_PKT_COPY_TILED_DW_6_x_offset 6 1085 #define SDMA_PKT_COPY_TILED_DW_6_x_mask 0x00003FFF 1086 #define SDMA_PKT_COPY_TILED_DW_6_x_shift 0 1087 #define SDMA_PKT_COPY_TILED_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_x_mask) << SDMA_PKT_COPY_TILED_DW_6_x_shift) 1088 1089 /*define for y field*/ 1090 #define SDMA_PKT_COPY_TILED_DW_6_y_offset 6 1091 #define SDMA_PKT_COPY_TILED_DW_6_y_mask 0x00003FFF 1092 #define SDMA_PKT_COPY_TILED_DW_6_y_shift 16 1093 #define SDMA_PKT_COPY_TILED_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_y_mask) << SDMA_PKT_COPY_TILED_DW_6_y_shift) 1094 1095 /*define for DW_7 word*/ 1096 /*define for z field*/ 1097 #define SDMA_PKT_COPY_TILED_DW_7_z_offset 7 1098 #define SDMA_PKT_COPY_TILED_DW_7_z_mask 0x00001FFF 1099 #define SDMA_PKT_COPY_TILED_DW_7_z_shift 0 1100 #define SDMA_PKT_COPY_TILED_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_z_mask) << SDMA_PKT_COPY_TILED_DW_7_z_shift) 1101 1102 /*define for linear_sw field*/ 1103 #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset 7 1104 #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask 0x00000003 1105 #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift 16 1106 #define SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift) 1107 1108 /*define for linear_cc field*/ 1109 #define SDMA_PKT_COPY_TILED_DW_7_linear_cc_offset 7 1110 #define SDMA_PKT_COPY_TILED_DW_7_linear_cc_mask 0x00000001 1111 #define SDMA_PKT_COPY_TILED_DW_7_linear_cc_shift 20 1112 #define SDMA_PKT_COPY_TILED_DW_7_LINEAR_CC(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_cc_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_cc_shift) 1113 1114 /*define for tile_sw field*/ 1115 #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset 7 1116 #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask 0x00000003 1117 #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift 24 1118 #define SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift) 1119 1120 /*define for LINEAR_ADDR_LO word*/ 1121 /*define for linear_addr_31_0 field*/ 1122 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset 8 1123 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 1124 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 1125 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift) 1126 1127 /*define for LINEAR_ADDR_HI word*/ 1128 /*define for linear_addr_63_32 field*/ 1129 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset 9 1130 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 1131 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 1132 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift) 1133 1134 /*define for LINEAR_PITCH word*/ 1135 /*define for linear_pitch field*/ 1136 #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset 10 1137 #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF 1138 #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift 0 1139 #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift) 1140 1141 /*define for LINEAR_SLICE_PITCH word*/ 1142 /*define for linear_slice_pitch field*/ 1143 #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 11 1144 #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF 1145 #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0 1146 #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) 1147 1148 /*define for COUNT word*/ 1149 /*define for count field*/ 1150 #define SDMA_PKT_COPY_TILED_COUNT_count_offset 12 1151 #define SDMA_PKT_COPY_TILED_COUNT_count_mask 0x003FFFFF 1152 #define SDMA_PKT_COPY_TILED_COUNT_count_shift 0 1153 #define SDMA_PKT_COPY_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_COUNT_count_mask) << SDMA_PKT_COPY_TILED_COUNT_count_shift) 1154 1155 1156 /* 1157 ** Definitions for SDMA_PKT_COPY_TILED_BC packet 1158 */ 1159 1160 /*define for HEADER word*/ 1161 /*define for op field*/ 1162 #define SDMA_PKT_COPY_TILED_BC_HEADER_op_offset 0 1163 #define SDMA_PKT_COPY_TILED_BC_HEADER_op_mask 0x000000FF 1164 #define SDMA_PKT_COPY_TILED_BC_HEADER_op_shift 0 1165 #define SDMA_PKT_COPY_TILED_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_op_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_op_shift) 1166 1167 /*define for sub_op field*/ 1168 #define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_offset 0 1169 #define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask 0x000000FF 1170 #define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift 8 1171 #define SDMA_PKT_COPY_TILED_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift) 1172 1173 /*define for detile field*/ 1174 #define SDMA_PKT_COPY_TILED_BC_HEADER_detile_offset 0 1175 #define SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask 0x00000001 1176 #define SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift 31 1177 #define SDMA_PKT_COPY_TILED_BC_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift) 1178 1179 /*define for TILED_ADDR_LO word*/ 1180 /*define for tiled_addr_31_0 field*/ 1181 #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_offset 1 1182 #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF 1183 #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift 0 1184 #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift) 1185 1186 /*define for TILED_ADDR_HI word*/ 1187 /*define for tiled_addr_63_32 field*/ 1188 #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_offset 2 1189 #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF 1190 #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift 0 1191 #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift) 1192 1193 /*define for DW_3 word*/ 1194 /*define for width field*/ 1195 #define SDMA_PKT_COPY_TILED_BC_DW_3_width_offset 3 1196 #define SDMA_PKT_COPY_TILED_BC_DW_3_width_mask 0x00003FFF 1197 #define SDMA_PKT_COPY_TILED_BC_DW_3_width_shift 0 1198 #define SDMA_PKT_COPY_TILED_BC_DW_3_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_3_width_mask) << SDMA_PKT_COPY_TILED_BC_DW_3_width_shift) 1199 1200 /*define for DW_4 word*/ 1201 /*define for height field*/ 1202 #define SDMA_PKT_COPY_TILED_BC_DW_4_height_offset 4 1203 #define SDMA_PKT_COPY_TILED_BC_DW_4_height_mask 0x00003FFF 1204 #define SDMA_PKT_COPY_TILED_BC_DW_4_height_shift 0 1205 #define SDMA_PKT_COPY_TILED_BC_DW_4_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_4_height_mask) << SDMA_PKT_COPY_TILED_BC_DW_4_height_shift) 1206 1207 /*define for depth field*/ 1208 #define SDMA_PKT_COPY_TILED_BC_DW_4_depth_offset 4 1209 #define SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask 0x000007FF 1210 #define SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift 16 1211 #define SDMA_PKT_COPY_TILED_BC_DW_4_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift) 1212 1213 /*define for DW_5 word*/ 1214 /*define for element_size field*/ 1215 #define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_offset 5 1216 #define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask 0x00000007 1217 #define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift 0 1218 #define SDMA_PKT_COPY_TILED_BC_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift) 1219 1220 /*define for array_mode field*/ 1221 #define SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_offset 5 1222 #define SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask 0x0000000F 1223 #define SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift 3 1224 #define SDMA_PKT_COPY_TILED_BC_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift) 1225 1226 /*define for mit_mode field*/ 1227 #define SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_offset 5 1228 #define SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask 0x00000007 1229 #define SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift 8 1230 #define SDMA_PKT_COPY_TILED_BC_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift) 1231 1232 /*define for tilesplit_size field*/ 1233 #define SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_offset 5 1234 #define SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask 0x00000007 1235 #define SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift 11 1236 #define SDMA_PKT_COPY_TILED_BC_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift) 1237 1238 /*define for bank_w field*/ 1239 #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_offset 5 1240 #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask 0x00000003 1241 #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift 15 1242 #define SDMA_PKT_COPY_TILED_BC_DW_5_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift) 1243 1244 /*define for bank_h field*/ 1245 #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_offset 5 1246 #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask 0x00000003 1247 #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift 18 1248 #define SDMA_PKT_COPY_TILED_BC_DW_5_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift) 1249 1250 /*define for num_bank field*/ 1251 #define SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_offset 5 1252 #define SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask 0x00000003 1253 #define SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift 21 1254 #define SDMA_PKT_COPY_TILED_BC_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift) 1255 1256 /*define for mat_aspt field*/ 1257 #define SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_offset 5 1258 #define SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask 0x00000003 1259 #define SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift 24 1260 #define SDMA_PKT_COPY_TILED_BC_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift) 1261 1262 /*define for pipe_config field*/ 1263 #define SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_offset 5 1264 #define SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask 0x0000001F 1265 #define SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift 26 1266 #define SDMA_PKT_COPY_TILED_BC_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift) 1267 1268 /*define for DW_6 word*/ 1269 /*define for x field*/ 1270 #define SDMA_PKT_COPY_TILED_BC_DW_6_x_offset 6 1271 #define SDMA_PKT_COPY_TILED_BC_DW_6_x_mask 0x00003FFF 1272 #define SDMA_PKT_COPY_TILED_BC_DW_6_x_shift 0 1273 #define SDMA_PKT_COPY_TILED_BC_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_6_x_mask) << SDMA_PKT_COPY_TILED_BC_DW_6_x_shift) 1274 1275 /*define for y field*/ 1276 #define SDMA_PKT_COPY_TILED_BC_DW_6_y_offset 6 1277 #define SDMA_PKT_COPY_TILED_BC_DW_6_y_mask 0x00003FFF 1278 #define SDMA_PKT_COPY_TILED_BC_DW_6_y_shift 16 1279 #define SDMA_PKT_COPY_TILED_BC_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_6_y_mask) << SDMA_PKT_COPY_TILED_BC_DW_6_y_shift) 1280 1281 /*define for DW_7 word*/ 1282 /*define for z field*/ 1283 #define SDMA_PKT_COPY_TILED_BC_DW_7_z_offset 7 1284 #define SDMA_PKT_COPY_TILED_BC_DW_7_z_mask 0x000007FF 1285 #define SDMA_PKT_COPY_TILED_BC_DW_7_z_shift 0 1286 #define SDMA_PKT_COPY_TILED_BC_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_z_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_z_shift) 1287 1288 /*define for linear_sw field*/ 1289 #define SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_offset 7 1290 #define SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask 0x00000003 1291 #define SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift 16 1292 #define SDMA_PKT_COPY_TILED_BC_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift) 1293 1294 /*define for tile_sw field*/ 1295 #define SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_offset 7 1296 #define SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask 0x00000003 1297 #define SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift 24 1298 #define SDMA_PKT_COPY_TILED_BC_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift) 1299 1300 /*define for LINEAR_ADDR_LO word*/ 1301 /*define for linear_addr_31_0 field*/ 1302 #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset 8 1303 #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 1304 #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 1305 #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift) 1306 1307 /*define for LINEAR_ADDR_HI word*/ 1308 /*define for linear_addr_63_32 field*/ 1309 #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset 9 1310 #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 1311 #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 1312 #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift) 1313 1314 /*define for LINEAR_PITCH word*/ 1315 /*define for linear_pitch field*/ 1316 #define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_offset 10 1317 #define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF 1318 #define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift 0 1319 #define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift) 1320 1321 /*define for COUNT word*/ 1322 /*define for count field*/ 1323 #define SDMA_PKT_COPY_TILED_BC_COUNT_count_offset 11 1324 #define SDMA_PKT_COPY_TILED_BC_COUNT_count_mask 0x000FFFFF 1325 #define SDMA_PKT_COPY_TILED_BC_COUNT_count_shift 2 1326 #define SDMA_PKT_COPY_TILED_BC_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_BC_COUNT_count_mask) << SDMA_PKT_COPY_TILED_BC_COUNT_count_shift) 1327 1328 1329 /* 1330 ** Definitions for SDMA_PKT_COPY_L2T_BROADCAST packet 1331 */ 1332 1333 /*define for HEADER word*/ 1334 /*define for op field*/ 1335 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset 0 1336 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask 0x000000FF 1337 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift 0 1338 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift) 1339 1340 /*define for sub_op field*/ 1341 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset 0 1342 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask 0x000000FF 1343 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift 8 1344 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift) 1345 1346 /*define for encrypt field*/ 1347 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset 0 1348 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask 0x00000001 1349 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift 16 1350 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift) 1351 1352 /*define for tmz field*/ 1353 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset 0 1354 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask 0x00000001 1355 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift 18 1356 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift) 1357 1358 /*define for videocopy field*/ 1359 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset 0 1360 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask 0x00000001 1361 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift 26 1362 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift) 1363 1364 /*define for broadcast field*/ 1365 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset 0 1366 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask 0x00000001 1367 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift 27 1368 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift) 1369 1370 /*define for TILED_ADDR_LO_0 word*/ 1371 /*define for tiled_addr0_31_0 field*/ 1372 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset 1 1373 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask 0xFFFFFFFF 1374 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift 0 1375 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift) 1376 1377 /*define for TILED_ADDR_HI_0 word*/ 1378 /*define for tiled_addr0_63_32 field*/ 1379 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset 2 1380 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask 0xFFFFFFFF 1381 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift 0 1382 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift) 1383 1384 /*define for TILED_ADDR_LO_1 word*/ 1385 /*define for tiled_addr1_31_0 field*/ 1386 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset 3 1387 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask 0xFFFFFFFF 1388 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift 0 1389 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift) 1390 1391 /*define for TILED_ADDR_HI_1 word*/ 1392 /*define for tiled_addr1_63_32 field*/ 1393 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset 4 1394 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask 0xFFFFFFFF 1395 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift 0 1396 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift) 1397 1398 /*define for DW_5 word*/ 1399 /*define for width field*/ 1400 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset 5 1401 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask 0x00003FFF 1402 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift 0 1403 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift) 1404 1405 /*define for DW_6 word*/ 1406 /*define for height field*/ 1407 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset 6 1408 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask 0x00003FFF 1409 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift 0 1410 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift) 1411 1412 /*define for depth field*/ 1413 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset 6 1414 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask 0x00001FFF 1415 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift 16 1416 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift) 1417 1418 /*define for DW_7 word*/ 1419 /*define for element_size field*/ 1420 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset 7 1421 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask 0x00000007 1422 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift 0 1423 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift) 1424 1425 /*define for swizzle_mode field*/ 1426 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset 7 1427 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask 0x0000001F 1428 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift 3 1429 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift) 1430 1431 /*define for dimension field*/ 1432 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset 7 1433 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask 0x00000003 1434 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift 9 1435 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift) 1436 1437 /*define for mip_max field*/ 1438 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_offset 7 1439 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask 0x0000000F 1440 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift 16 1441 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MIP_MAX(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift) 1442 1443 /*define for DW_8 word*/ 1444 /*define for x field*/ 1445 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset 8 1446 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask 0x00003FFF 1447 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift 0 1448 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift) 1449 1450 /*define for y field*/ 1451 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset 8 1452 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask 0x00003FFF 1453 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift 16 1454 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift) 1455 1456 /*define for DW_9 word*/ 1457 /*define for z field*/ 1458 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset 9 1459 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask 0x00001FFF 1460 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift 0 1461 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift) 1462 1463 /*define for DW_10 word*/ 1464 /*define for dst2_sw field*/ 1465 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset 10 1466 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask 0x00000003 1467 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift 8 1468 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift) 1469 1470 /*define for linear_sw field*/ 1471 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset 10 1472 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask 0x00000003 1473 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift 16 1474 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift) 1475 1476 /*define for tile_sw field*/ 1477 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset 10 1478 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask 0x00000003 1479 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift 24 1480 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift) 1481 1482 /*define for LINEAR_ADDR_LO word*/ 1483 /*define for linear_addr_31_0 field*/ 1484 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset 11 1485 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 1486 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 1487 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift) 1488 1489 /*define for LINEAR_ADDR_HI word*/ 1490 /*define for linear_addr_63_32 field*/ 1491 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset 12 1492 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 1493 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 1494 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift) 1495 1496 /*define for LINEAR_PITCH word*/ 1497 /*define for linear_pitch field*/ 1498 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset 13 1499 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF 1500 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift 0 1501 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift) 1502 1503 /*define for LINEAR_SLICE_PITCH word*/ 1504 /*define for linear_slice_pitch field*/ 1505 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 14 1506 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF 1507 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0 1508 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) 1509 1510 /*define for COUNT word*/ 1511 /*define for count field*/ 1512 #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset 15 1513 #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask 0x003FFFFF 1514 #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift 0 1515 #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask) << SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift) 1516 1517 1518 /* 1519 ** Definitions for SDMA_PKT_COPY_T2T packet 1520 */ 1521 1522 /*define for HEADER word*/ 1523 /*define for op field*/ 1524 #define SDMA_PKT_COPY_T2T_HEADER_op_offset 0 1525 #define SDMA_PKT_COPY_T2T_HEADER_op_mask 0x000000FF 1526 #define SDMA_PKT_COPY_T2T_HEADER_op_shift 0 1527 #define SDMA_PKT_COPY_T2T_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_op_mask) << SDMA_PKT_COPY_T2T_HEADER_op_shift) 1528 1529 /*define for sub_op field*/ 1530 #define SDMA_PKT_COPY_T2T_HEADER_sub_op_offset 0 1531 #define SDMA_PKT_COPY_T2T_HEADER_sub_op_mask 0x000000FF 1532 #define SDMA_PKT_COPY_T2T_HEADER_sub_op_shift 8 1533 #define SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_HEADER_sub_op_shift) 1534 1535 /*define for tmz field*/ 1536 #define SDMA_PKT_COPY_T2T_HEADER_tmz_offset 0 1537 #define SDMA_PKT_COPY_T2T_HEADER_tmz_mask 0x00000001 1538 #define SDMA_PKT_COPY_T2T_HEADER_tmz_shift 18 1539 #define SDMA_PKT_COPY_T2T_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_tmz_mask) << SDMA_PKT_COPY_T2T_HEADER_tmz_shift) 1540 1541 /*define for dcc field*/ 1542 #define SDMA_PKT_COPY_T2T_HEADER_dcc_offset 0 1543 #define SDMA_PKT_COPY_T2T_HEADER_dcc_mask 0x00000001 1544 #define SDMA_PKT_COPY_T2T_HEADER_dcc_shift 19 1545 #define SDMA_PKT_COPY_T2T_HEADER_DCC(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_dcc_mask) << SDMA_PKT_COPY_T2T_HEADER_dcc_shift) 1546 1547 /*define for dcc_dir field*/ 1548 #define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_offset 0 1549 #define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask 0x00000001 1550 #define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift 31 1551 #define SDMA_PKT_COPY_T2T_HEADER_DCC_DIR(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask) << SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift) 1552 1553 /*define for SRC_ADDR_LO word*/ 1554 /*define for src_addr_31_0 field*/ 1555 #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset 1 1556 #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 1557 #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift 0 1558 #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift) 1559 1560 /*define for SRC_ADDR_HI word*/ 1561 /*define for src_addr_63_32 field*/ 1562 #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset 2 1563 #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 1564 #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift 0 1565 #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift) 1566 1567 /*define for DW_3 word*/ 1568 /*define for src_x field*/ 1569 #define SDMA_PKT_COPY_T2T_DW_3_src_x_offset 3 1570 #define SDMA_PKT_COPY_T2T_DW_3_src_x_mask 0x00003FFF 1571 #define SDMA_PKT_COPY_T2T_DW_3_src_x_shift 0 1572 #define SDMA_PKT_COPY_T2T_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_DW_3_src_x_shift) 1573 1574 /*define for src_y field*/ 1575 #define SDMA_PKT_COPY_T2T_DW_3_src_y_offset 3 1576 #define SDMA_PKT_COPY_T2T_DW_3_src_y_mask 0x00003FFF 1577 #define SDMA_PKT_COPY_T2T_DW_3_src_y_shift 16 1578 #define SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_DW_3_src_y_shift) 1579 1580 /*define for DW_4 word*/ 1581 /*define for src_z field*/ 1582 #define SDMA_PKT_COPY_T2T_DW_4_src_z_offset 4 1583 #define SDMA_PKT_COPY_T2T_DW_4_src_z_mask 0x00001FFF 1584 #define SDMA_PKT_COPY_T2T_DW_4_src_z_shift 0 1585 #define SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_DW_4_src_z_shift) 1586 1587 /*define for src_width field*/ 1588 #define SDMA_PKT_COPY_T2T_DW_4_src_width_offset 4 1589 #define SDMA_PKT_COPY_T2T_DW_4_src_width_mask 0x00003FFF 1590 #define SDMA_PKT_COPY_T2T_DW_4_src_width_shift 16 1591 #define SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_DW_4_src_width_shift) 1592 1593 /*define for DW_5 word*/ 1594 /*define for src_height field*/ 1595 #define SDMA_PKT_COPY_T2T_DW_5_src_height_offset 5 1596 #define SDMA_PKT_COPY_T2T_DW_5_src_height_mask 0x00003FFF 1597 #define SDMA_PKT_COPY_T2T_DW_5_src_height_shift 0 1598 #define SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_DW_5_src_height_shift) 1599 1600 /*define for src_depth field*/ 1601 #define SDMA_PKT_COPY_T2T_DW_5_src_depth_offset 5 1602 #define SDMA_PKT_COPY_T2T_DW_5_src_depth_mask 0x00001FFF 1603 #define SDMA_PKT_COPY_T2T_DW_5_src_depth_shift 16 1604 #define SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_DW_5_src_depth_shift) 1605 1606 /*define for DW_6 word*/ 1607 /*define for src_element_size field*/ 1608 #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset 6 1609 #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask 0x00000007 1610 #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift 0 1611 #define SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift) 1612 1613 /*define for src_swizzle_mode field*/ 1614 #define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset 6 1615 #define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask 0x0000001F 1616 #define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift 3 1617 #define SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift) 1618 1619 /*define for src_dimension field*/ 1620 #define SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset 6 1621 #define SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask 0x00000003 1622 #define SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift 9 1623 #define SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask) << SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift) 1624 1625 /*define for src_mip_max field*/ 1626 #define SDMA_PKT_COPY_T2T_DW_6_src_mip_max_offset 6 1627 #define SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask 0x0000000F 1628 #define SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift 16 1629 #define SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_MAX(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift) 1630 1631 /*define for src_mip_id field*/ 1632 #define SDMA_PKT_COPY_T2T_DW_6_src_mip_id_offset 6 1633 #define SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask 0x0000000F 1634 #define SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift 20 1635 #define SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_ID(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift) 1636 1637 /*define for DST_ADDR_LO word*/ 1638 /*define for dst_addr_31_0 field*/ 1639 #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset 7 1640 #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 1641 #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift 0 1642 #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift) 1643 1644 /*define for DST_ADDR_HI word*/ 1645 /*define for dst_addr_63_32 field*/ 1646 #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset 8 1647 #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 1648 #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift 0 1649 #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift) 1650 1651 /*define for DW_9 word*/ 1652 /*define for dst_x field*/ 1653 #define SDMA_PKT_COPY_T2T_DW_9_dst_x_offset 9 1654 #define SDMA_PKT_COPY_T2T_DW_9_dst_x_mask 0x00003FFF 1655 #define SDMA_PKT_COPY_T2T_DW_9_dst_x_shift 0 1656 #define SDMA_PKT_COPY_T2T_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_x_shift) 1657 1658 /*define for dst_y field*/ 1659 #define SDMA_PKT_COPY_T2T_DW_9_dst_y_offset 9 1660 #define SDMA_PKT_COPY_T2T_DW_9_dst_y_mask 0x00003FFF 1661 #define SDMA_PKT_COPY_T2T_DW_9_dst_y_shift 16 1662 #define SDMA_PKT_COPY_T2T_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_y_shift) 1663 1664 /*define for DW_10 word*/ 1665 /*define for dst_z field*/ 1666 #define SDMA_PKT_COPY_T2T_DW_10_dst_z_offset 10 1667 #define SDMA_PKT_COPY_T2T_DW_10_dst_z_mask 0x00001FFF 1668 #define SDMA_PKT_COPY_T2T_DW_10_dst_z_shift 0 1669 #define SDMA_PKT_COPY_T2T_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_z_shift) 1670 1671 /*define for dst_width field*/ 1672 #define SDMA_PKT_COPY_T2T_DW_10_dst_width_offset 10 1673 #define SDMA_PKT_COPY_T2T_DW_10_dst_width_mask 0x00003FFF 1674 #define SDMA_PKT_COPY_T2T_DW_10_dst_width_shift 16 1675 #define SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_width_shift) 1676 1677 /*define for DW_11 word*/ 1678 /*define for dst_height field*/ 1679 #define SDMA_PKT_COPY_T2T_DW_11_dst_height_offset 11 1680 #define SDMA_PKT_COPY_T2T_DW_11_dst_height_mask 0x00003FFF 1681 #define SDMA_PKT_COPY_T2T_DW_11_dst_height_shift 0 1682 #define SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_height_shift) 1683 1684 /*define for dst_depth field*/ 1685 #define SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset 11 1686 #define SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask 0x00001FFF 1687 #define SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift 16 1688 #define SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift) 1689 1690 /*define for DW_12 word*/ 1691 /*define for dst_element_size field*/ 1692 #define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset 12 1693 #define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask 0x00000007 1694 #define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift 0 1695 #define SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift) 1696 1697 /*define for dst_swizzle_mode field*/ 1698 #define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset 12 1699 #define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask 0x0000001F 1700 #define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift 3 1701 #define SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift) 1702 1703 /*define for dst_dimension field*/ 1704 #define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset 12 1705 #define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask 0x00000003 1706 #define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift 9 1707 #define SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift) 1708 1709 /*define for dst_mip_max field*/ 1710 #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_offset 12 1711 #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask 0x0000000F 1712 #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift 16 1713 #define SDMA_PKT_COPY_T2T_DW_12_DST_MIP_MAX(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift) 1714 1715 /*define for dst_mip_id field*/ 1716 #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_offset 12 1717 #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask 0x0000000F 1718 #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift 20 1719 #define SDMA_PKT_COPY_T2T_DW_12_DST_MIP_ID(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift) 1720 1721 /*define for DW_13 word*/ 1722 /*define for rect_x field*/ 1723 #define SDMA_PKT_COPY_T2T_DW_13_rect_x_offset 13 1724 #define SDMA_PKT_COPY_T2T_DW_13_rect_x_mask 0x00003FFF 1725 #define SDMA_PKT_COPY_T2T_DW_13_rect_x_shift 0 1726 #define SDMA_PKT_COPY_T2T_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_x_shift) 1727 1728 /*define for rect_y field*/ 1729 #define SDMA_PKT_COPY_T2T_DW_13_rect_y_offset 13 1730 #define SDMA_PKT_COPY_T2T_DW_13_rect_y_mask 0x00003FFF 1731 #define SDMA_PKT_COPY_T2T_DW_13_rect_y_shift 16 1732 #define SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_y_shift) 1733 1734 /*define for DW_14 word*/ 1735 /*define for rect_z field*/ 1736 #define SDMA_PKT_COPY_T2T_DW_14_rect_z_offset 14 1737 #define SDMA_PKT_COPY_T2T_DW_14_rect_z_mask 0x00001FFF 1738 #define SDMA_PKT_COPY_T2T_DW_14_rect_z_shift 0 1739 #define SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_DW_14_rect_z_shift) 1740 1741 /*define for dst_sw field*/ 1742 #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset 14 1743 #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask 0x00000003 1744 #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift 16 1745 #define SDMA_PKT_COPY_T2T_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift) 1746 1747 /*define for src_sw field*/ 1748 #define SDMA_PKT_COPY_T2T_DW_14_src_sw_offset 14 1749 #define SDMA_PKT_COPY_T2T_DW_14_src_sw_mask 0x00000003 1750 #define SDMA_PKT_COPY_T2T_DW_14_src_sw_shift 24 1751 #define SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_src_sw_shift) 1752 1753 /*define for META_ADDR_LO word*/ 1754 /*define for meta_addr_31_0 field*/ 1755 #define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_offset 15 1756 #define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask 0xFFFFFFFF 1757 #define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift 0 1758 #define SDMA_PKT_COPY_T2T_META_ADDR_LO_META_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask) << SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift) 1759 1760 /*define for META_ADDR_HI word*/ 1761 /*define for meta_addr_63_32 field*/ 1762 #define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_offset 16 1763 #define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask 0xFFFFFFFF 1764 #define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift 0 1765 #define SDMA_PKT_COPY_T2T_META_ADDR_HI_META_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask) << SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift) 1766 1767 /*define for META_CONFIG word*/ 1768 /*define for data_format field*/ 1769 #define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_offset 17 1770 #define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask 0x0000007F 1771 #define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift 0 1772 #define SDMA_PKT_COPY_T2T_META_CONFIG_DATA_FORMAT(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift) 1773 1774 /*define for color_transform_disable field*/ 1775 #define SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_offset 17 1776 #define SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask 0x00000001 1777 #define SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift 7 1778 #define SDMA_PKT_COPY_T2T_META_CONFIG_COLOR_TRANSFORM_DISABLE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift) 1779 1780 /*define for alpha_is_on_msb field*/ 1781 #define SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_offset 17 1782 #define SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask 0x00000001 1783 #define SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift 8 1784 #define SDMA_PKT_COPY_T2T_META_CONFIG_ALPHA_IS_ON_MSB(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift) 1785 1786 /*define for number_type field*/ 1787 #define SDMA_PKT_COPY_T2T_META_CONFIG_number_type_offset 17 1788 #define SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask 0x00000007 1789 #define SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift 9 1790 #define SDMA_PKT_COPY_T2T_META_CONFIG_NUMBER_TYPE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift) 1791 1792 /*define for surface_type field*/ 1793 #define SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_offset 17 1794 #define SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask 0x00000003 1795 #define SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift 12 1796 #define SDMA_PKT_COPY_T2T_META_CONFIG_SURFACE_TYPE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift) 1797 1798 /*define for max_comp_block_size field*/ 1799 #define SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_offset 17 1800 #define SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask 0x00000003 1801 #define SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift 24 1802 #define SDMA_PKT_COPY_T2T_META_CONFIG_MAX_COMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift) 1803 1804 /*define for max_uncomp_block_size field*/ 1805 #define SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_offset 17 1806 #define SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask 0x00000003 1807 #define SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift 26 1808 #define SDMA_PKT_COPY_T2T_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift) 1809 1810 /*define for write_compress_enable field*/ 1811 #define SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_offset 17 1812 #define SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask 0x00000001 1813 #define SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift 28 1814 #define SDMA_PKT_COPY_T2T_META_CONFIG_WRITE_COMPRESS_ENABLE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift) 1815 1816 /*define for meta_tmz field*/ 1817 #define SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_offset 17 1818 #define SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask 0x00000001 1819 #define SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift 29 1820 #define SDMA_PKT_COPY_T2T_META_CONFIG_META_TMZ(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift) 1821 1822 1823 /* 1824 ** Definitions for SDMA_PKT_COPY_T2T_BC packet 1825 */ 1826 1827 /*define for HEADER word*/ 1828 /*define for op field*/ 1829 #define SDMA_PKT_COPY_T2T_BC_HEADER_op_offset 0 1830 #define SDMA_PKT_COPY_T2T_BC_HEADER_op_mask 0x000000FF 1831 #define SDMA_PKT_COPY_T2T_BC_HEADER_op_shift 0 1832 #define SDMA_PKT_COPY_T2T_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_BC_HEADER_op_mask) << SDMA_PKT_COPY_T2T_BC_HEADER_op_shift) 1833 1834 /*define for sub_op field*/ 1835 #define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_offset 0 1836 #define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask 0x000000FF 1837 #define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift 8 1838 #define SDMA_PKT_COPY_T2T_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift) 1839 1840 /*define for SRC_ADDR_LO word*/ 1841 /*define for src_addr_31_0 field*/ 1842 #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_offset 1 1843 #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 1844 #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift 0 1845 #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift) 1846 1847 /*define for SRC_ADDR_HI word*/ 1848 /*define for src_addr_63_32 field*/ 1849 #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_offset 2 1850 #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 1851 #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift 0 1852 #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift) 1853 1854 /*define for DW_3 word*/ 1855 /*define for src_x field*/ 1856 #define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_offset 3 1857 #define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask 0x00003FFF 1858 #define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift 0 1859 #define SDMA_PKT_COPY_T2T_BC_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift) 1860 1861 /*define for src_y field*/ 1862 #define SDMA_PKT_COPY_T2T_BC_DW_3_src_y_offset 3 1863 #define SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask 0x00003FFF 1864 #define SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift 16 1865 #define SDMA_PKT_COPY_T2T_BC_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift) 1866 1867 /*define for DW_4 word*/ 1868 /*define for src_z field*/ 1869 #define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_offset 4 1870 #define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask 0x000007FF 1871 #define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift 0 1872 #define SDMA_PKT_COPY_T2T_BC_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift) 1873 1874 /*define for src_width field*/ 1875 #define SDMA_PKT_COPY_T2T_BC_DW_4_src_width_offset 4 1876 #define SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask 0x00003FFF 1877 #define SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift 16 1878 #define SDMA_PKT_COPY_T2T_BC_DW_4_SRC_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift) 1879 1880 /*define for DW_5 word*/ 1881 /*define for src_height field*/ 1882 #define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_offset 5 1883 #define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask 0x00003FFF 1884 #define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift 0 1885 #define SDMA_PKT_COPY_T2T_BC_DW_5_SRC_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift) 1886 1887 /*define for src_depth field*/ 1888 #define SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_offset 5 1889 #define SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask 0x000007FF 1890 #define SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift 16 1891 #define SDMA_PKT_COPY_T2T_BC_DW_5_SRC_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift) 1892 1893 /*define for DW_6 word*/ 1894 /*define for src_element_size field*/ 1895 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_offset 6 1896 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask 0x00000007 1897 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift 0 1898 #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift) 1899 1900 /*define for src_array_mode field*/ 1901 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_offset 6 1902 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask 0x0000000F 1903 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift 3 1904 #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift) 1905 1906 /*define for src_mit_mode field*/ 1907 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_offset 6 1908 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask 0x00000007 1909 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift 8 1910 #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift) 1911 1912 /*define for src_tilesplit_size field*/ 1913 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_offset 6 1914 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask 0x00000007 1915 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift 11 1916 #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift) 1917 1918 /*define for src_bank_w field*/ 1919 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_offset 6 1920 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask 0x00000003 1921 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift 15 1922 #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift) 1923 1924 /*define for src_bank_h field*/ 1925 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_offset 6 1926 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask 0x00000003 1927 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift 18 1928 #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift) 1929 1930 /*define for src_num_bank field*/ 1931 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_offset 6 1932 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask 0x00000003 1933 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift 21 1934 #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift) 1935 1936 /*define for src_mat_aspt field*/ 1937 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_offset 6 1938 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask 0x00000003 1939 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift 24 1940 #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift) 1941 1942 /*define for src_pipe_config field*/ 1943 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_offset 6 1944 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask 0x0000001F 1945 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift 26 1946 #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift) 1947 1948 /*define for DST_ADDR_LO word*/ 1949 /*define for dst_addr_31_0 field*/ 1950 #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_offset 7 1951 #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 1952 #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 1953 #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift) 1954 1955 /*define for DST_ADDR_HI word*/ 1956 /*define for dst_addr_63_32 field*/ 1957 #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_offset 8 1958 #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 1959 #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 1960 #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift) 1961 1962 /*define for DW_9 word*/ 1963 /*define for dst_x field*/ 1964 #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_offset 9 1965 #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask 0x00003FFF 1966 #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift 0 1967 #define SDMA_PKT_COPY_T2T_BC_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift) 1968 1969 /*define for dst_y field*/ 1970 #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_offset 9 1971 #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask 0x00003FFF 1972 #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift 16 1973 #define SDMA_PKT_COPY_T2T_BC_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift) 1974 1975 /*define for DW_10 word*/ 1976 /*define for dst_z field*/ 1977 #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_offset 10 1978 #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask 0x000007FF 1979 #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift 0 1980 #define SDMA_PKT_COPY_T2T_BC_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift) 1981 1982 /*define for dst_width field*/ 1983 #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_offset 10 1984 #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask 0x00003FFF 1985 #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift 16 1986 #define SDMA_PKT_COPY_T2T_BC_DW_10_DST_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift) 1987 1988 /*define for DW_11 word*/ 1989 /*define for dst_height field*/ 1990 #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_offset 11 1991 #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask 0x00003FFF 1992 #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift 0 1993 #define SDMA_PKT_COPY_T2T_BC_DW_11_DST_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift) 1994 1995 /*define for dst_depth field*/ 1996 #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_offset 11 1997 #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask 0x00000FFF 1998 #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift 16 1999 #define SDMA_PKT_COPY_T2T_BC_DW_11_DST_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift) 2000 2001 /*define for DW_12 word*/ 2002 /*define for dst_element_size field*/ 2003 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_offset 12 2004 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask 0x00000007 2005 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift 0 2006 #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift) 2007 2008 /*define for dst_array_mode field*/ 2009 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_offset 12 2010 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask 0x0000000F 2011 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift 3 2012 #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift) 2013 2014 /*define for dst_mit_mode field*/ 2015 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_offset 12 2016 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask 0x00000007 2017 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift 8 2018 #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift) 2019 2020 /*define for dst_tilesplit_size field*/ 2021 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_offset 12 2022 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask 0x00000007 2023 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift 11 2024 #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift) 2025 2026 /*define for dst_bank_w field*/ 2027 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_offset 12 2028 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask 0x00000003 2029 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift 15 2030 #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift) 2031 2032 /*define for dst_bank_h field*/ 2033 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_offset 12 2034 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask 0x00000003 2035 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift 18 2036 #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift) 2037 2038 /*define for dst_num_bank field*/ 2039 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_offset 12 2040 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask 0x00000003 2041 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift 21 2042 #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift) 2043 2044 /*define for dst_mat_aspt field*/ 2045 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_offset 12 2046 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask 0x00000003 2047 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift 24 2048 #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift) 2049 2050 /*define for dst_pipe_config field*/ 2051 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_offset 12 2052 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask 0x0000001F 2053 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift 26 2054 #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift) 2055 2056 /*define for DW_13 word*/ 2057 /*define for rect_x field*/ 2058 #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_offset 13 2059 #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask 0x00003FFF 2060 #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift 0 2061 #define SDMA_PKT_COPY_T2T_BC_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift) 2062 2063 /*define for rect_y field*/ 2064 #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_offset 13 2065 #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask 0x00003FFF 2066 #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift 16 2067 #define SDMA_PKT_COPY_T2T_BC_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift) 2068 2069 /*define for DW_14 word*/ 2070 /*define for rect_z field*/ 2071 #define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_offset 14 2072 #define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask 0x000007FF 2073 #define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift 0 2074 #define SDMA_PKT_COPY_T2T_BC_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift) 2075 2076 /*define for dst_sw field*/ 2077 #define SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_offset 14 2078 #define SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask 0x00000003 2079 #define SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift 16 2080 #define SDMA_PKT_COPY_T2T_BC_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift) 2081 2082 /*define for src_sw field*/ 2083 #define SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_offset 14 2084 #define SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask 0x00000003 2085 #define SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift 24 2086 #define SDMA_PKT_COPY_T2T_BC_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift) 2087 2088 2089 /* 2090 ** Definitions for SDMA_PKT_COPY_TILED_SUBWIN packet 2091 */ 2092 2093 /*define for HEADER word*/ 2094 /*define for op field*/ 2095 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset 0 2096 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask 0x000000FF 2097 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift 0 2098 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift) 2099 2100 /*define for sub_op field*/ 2101 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset 0 2102 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask 0x000000FF 2103 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift 8 2104 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift) 2105 2106 /*define for tmz field*/ 2107 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset 0 2108 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask 0x00000001 2109 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift 18 2110 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift) 2111 2112 /*define for dcc field*/ 2113 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_offset 0 2114 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask 0x00000001 2115 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift 19 2116 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DCC(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift) 2117 2118 /*define for detile field*/ 2119 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset 0 2120 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask 0x00000001 2121 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift 31 2122 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift) 2123 2124 /*define for TILED_ADDR_LO word*/ 2125 /*define for tiled_addr_31_0 field*/ 2126 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset 1 2127 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF 2128 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift 0 2129 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift) 2130 2131 /*define for TILED_ADDR_HI word*/ 2132 /*define for tiled_addr_63_32 field*/ 2133 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset 2 2134 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF 2135 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift 0 2136 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift) 2137 2138 /*define for DW_3 word*/ 2139 /*define for tiled_x field*/ 2140 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset 3 2141 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask 0x00003FFF 2142 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift 0 2143 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift) 2144 2145 /*define for tiled_y field*/ 2146 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset 3 2147 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask 0x00003FFF 2148 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift 16 2149 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift) 2150 2151 /*define for DW_4 word*/ 2152 /*define for tiled_z field*/ 2153 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset 4 2154 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask 0x00001FFF 2155 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift 0 2156 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift) 2157 2158 /*define for width field*/ 2159 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset 4 2160 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask 0x00003FFF 2161 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift 16 2162 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift) 2163 2164 /*define for DW_5 word*/ 2165 /*define for height field*/ 2166 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset 5 2167 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask 0x00003FFF 2168 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift 0 2169 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift) 2170 2171 /*define for depth field*/ 2172 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset 5 2173 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask 0x00001FFF 2174 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift 16 2175 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift) 2176 2177 /*define for DW_6 word*/ 2178 /*define for element_size field*/ 2179 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset 6 2180 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask 0x00000007 2181 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift 0 2182 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift) 2183 2184 /*define for swizzle_mode field*/ 2185 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset 6 2186 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask 0x0000001F 2187 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift 3 2188 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift) 2189 2190 /*define for dimension field*/ 2191 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset 6 2192 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask 0x00000003 2193 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift 9 2194 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift) 2195 2196 /*define for mip_max field*/ 2197 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_offset 6 2198 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask 0x0000000F 2199 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift 16 2200 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift) 2201 2202 /*define for mip_id field*/ 2203 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_offset 6 2204 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask 0x0000000F 2205 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift 20 2206 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_ID(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift) 2207 2208 /*define for LINEAR_ADDR_LO word*/ 2209 /*define for linear_addr_31_0 field*/ 2210 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset 7 2211 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 2212 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 2213 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift) 2214 2215 /*define for LINEAR_ADDR_HI word*/ 2216 /*define for linear_addr_63_32 field*/ 2217 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset 8 2218 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 2219 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 2220 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift) 2221 2222 /*define for DW_9 word*/ 2223 /*define for linear_x field*/ 2224 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset 9 2225 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask 0x00003FFF 2226 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift 0 2227 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift) 2228 2229 /*define for linear_y field*/ 2230 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset 9 2231 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask 0x00003FFF 2232 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift 16 2233 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift) 2234 2235 /*define for DW_10 word*/ 2236 /*define for linear_z field*/ 2237 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset 10 2238 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask 0x00001FFF 2239 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift 0 2240 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift) 2241 2242 /*define for linear_pitch field*/ 2243 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset 10 2244 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask 0x00003FFF 2245 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift 16 2246 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift) 2247 2248 /*define for DW_11 word*/ 2249 /*define for linear_slice_pitch field*/ 2250 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset 11 2251 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask 0x0FFFFFFF 2252 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift 0 2253 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift) 2254 2255 /*define for DW_12 word*/ 2256 /*define for rect_x field*/ 2257 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset 12 2258 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask 0x00003FFF 2259 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift 0 2260 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift) 2261 2262 /*define for rect_y field*/ 2263 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset 12 2264 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask 0x00003FFF 2265 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift 16 2266 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift) 2267 2268 /*define for DW_13 word*/ 2269 /*define for rect_z field*/ 2270 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset 13 2271 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask 0x00001FFF 2272 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift 0 2273 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift) 2274 2275 /*define for linear_sw field*/ 2276 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset 13 2277 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask 0x00000003 2278 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift 16 2279 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift) 2280 2281 /*define for tile_sw field*/ 2282 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset 13 2283 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask 0x00000003 2284 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift 24 2285 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift) 2286 2287 /*define for META_ADDR_LO word*/ 2288 /*define for meta_addr_31_0 field*/ 2289 #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_offset 14 2290 #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask 0xFFFFFFFF 2291 #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift 0 2292 #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_META_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift) 2293 2294 /*define for META_ADDR_HI word*/ 2295 /*define for meta_addr_63_32 field*/ 2296 #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_offset 15 2297 #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask 0xFFFFFFFF 2298 #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift 0 2299 #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_META_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift) 2300 2301 /*define for META_CONFIG word*/ 2302 /*define for data_format field*/ 2303 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_offset 16 2304 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask 0x0000007F 2305 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift 0 2306 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_DATA_FORMAT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift) 2307 2308 /*define for color_transform_disable field*/ 2309 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_offset 16 2310 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask 0x00000001 2311 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift 7 2312 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_COLOR_TRANSFORM_DISABLE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift) 2313 2314 /*define for alpha_is_on_msb field*/ 2315 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_offset 16 2316 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask 0x00000001 2317 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift 8 2318 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_ALPHA_IS_ON_MSB(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift) 2319 2320 /*define for number_type field*/ 2321 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_offset 16 2322 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask 0x00000007 2323 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift 9 2324 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_NUMBER_TYPE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift) 2325 2326 /*define for surface_type field*/ 2327 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_offset 16 2328 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask 0x00000003 2329 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift 12 2330 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_SURFACE_TYPE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift) 2331 2332 /*define for max_comp_block_size field*/ 2333 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_offset 16 2334 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask 0x00000003 2335 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift 24 2336 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_COMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift) 2337 2338 /*define for max_uncomp_block_size field*/ 2339 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_offset 16 2340 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask 0x00000003 2341 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift 26 2342 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift) 2343 2344 /*define for write_compress_enable field*/ 2345 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_offset 16 2346 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask 0x00000001 2347 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift 28 2348 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_WRITE_COMPRESS_ENABLE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift) 2349 2350 /*define for meta_tmz field*/ 2351 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_offset 16 2352 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask 0x00000001 2353 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift 29 2354 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_META_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift) 2355 2356 2357 /* 2358 ** Definitions for SDMA_PKT_COPY_TILED_SUBWIN_BC packet 2359 */ 2360 2361 /*define for HEADER word*/ 2362 /*define for op field*/ 2363 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_offset 0 2364 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask 0x000000FF 2365 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift 0 2366 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift) 2367 2368 /*define for sub_op field*/ 2369 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_offset 0 2370 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask 0x000000FF 2371 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift 8 2372 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift) 2373 2374 /*define for detile field*/ 2375 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_offset 0 2376 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask 0x00000001 2377 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift 31 2378 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift) 2379 2380 /*define for TILED_ADDR_LO word*/ 2381 /*define for tiled_addr_31_0 field*/ 2382 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_offset 1 2383 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF 2384 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift 0 2385 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift) 2386 2387 /*define for TILED_ADDR_HI word*/ 2388 /*define for tiled_addr_63_32 field*/ 2389 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_offset 2 2390 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF 2391 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift 0 2392 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift) 2393 2394 /*define for DW_3 word*/ 2395 /*define for tiled_x field*/ 2396 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_offset 3 2397 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask 0x00003FFF 2398 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift 0 2399 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift) 2400 2401 /*define for tiled_y field*/ 2402 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_offset 3 2403 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask 0x00003FFF 2404 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift 16 2405 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift) 2406 2407 /*define for DW_4 word*/ 2408 /*define for tiled_z field*/ 2409 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_offset 4 2410 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask 0x000007FF 2411 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift 0 2412 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift) 2413 2414 /*define for width field*/ 2415 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_offset 4 2416 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask 0x00003FFF 2417 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift 16 2418 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift) 2419 2420 /*define for DW_5 word*/ 2421 /*define for height field*/ 2422 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_offset 5 2423 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask 0x00003FFF 2424 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift 0 2425 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift) 2426 2427 /*define for depth field*/ 2428 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_offset 5 2429 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask 0x000007FF 2430 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift 16 2431 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift) 2432 2433 /*define for DW_6 word*/ 2434 /*define for element_size field*/ 2435 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_offset 6 2436 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask 0x00000007 2437 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift 0 2438 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift) 2439 2440 /*define for array_mode field*/ 2441 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_offset 6 2442 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask 0x0000000F 2443 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift 3 2444 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift) 2445 2446 /*define for mit_mode field*/ 2447 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_offset 6 2448 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask 0x00000007 2449 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift 8 2450 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift) 2451 2452 /*define for tilesplit_size field*/ 2453 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_offset 6 2454 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask 0x00000007 2455 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift 11 2456 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift) 2457 2458 /*define for bank_w field*/ 2459 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_offset 6 2460 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask 0x00000003 2461 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift 15 2462 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift) 2463 2464 /*define for bank_h field*/ 2465 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_offset 6 2466 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask 0x00000003 2467 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift 18 2468 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift) 2469 2470 /*define for num_bank field*/ 2471 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_offset 6 2472 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask 0x00000003 2473 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift 21 2474 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift) 2475 2476 /*define for mat_aspt field*/ 2477 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_offset 6 2478 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask 0x00000003 2479 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift 24 2480 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MAT_ASPT(x) ((x & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift) 2481 2482 /*define for pipe_config field*/ 2483 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_offset 6 2484 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask 0x0000001F 2485 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift 26 2486 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift) 2487 2488 /*define for LINEAR_ADDR_LO word*/ 2489 /*define for linear_addr_31_0 field*/ 2490 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset 7 2491 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 2492 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 2493 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift) 2494 2495 /*define for LINEAR_ADDR_HI word*/ 2496 /*define for linear_addr_63_32 field*/ 2497 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset 8 2498 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 2499 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 2500 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift) 2501 2502 /*define for DW_9 word*/ 2503 /*define for linear_x field*/ 2504 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_offset 9 2505 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask 0x00003FFF 2506 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift 0 2507 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift) 2508 2509 /*define for linear_y field*/ 2510 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_offset 9 2511 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask 0x00003FFF 2512 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift 16 2513 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift) 2514 2515 /*define for DW_10 word*/ 2516 /*define for linear_z field*/ 2517 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_offset 10 2518 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask 0x000007FF 2519 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift 0 2520 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift) 2521 2522 /*define for linear_pitch field*/ 2523 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_offset 10 2524 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask 0x00003FFF 2525 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift 16 2526 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift) 2527 2528 /*define for DW_11 word*/ 2529 /*define for linear_slice_pitch field*/ 2530 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_offset 11 2531 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask 0x0FFFFFFF 2532 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift 0 2533 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift) 2534 2535 /*define for DW_12 word*/ 2536 /*define for rect_x field*/ 2537 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_offset 12 2538 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask 0x00003FFF 2539 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift 0 2540 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift) 2541 2542 /*define for rect_y field*/ 2543 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_offset 12 2544 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask 0x00003FFF 2545 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift 16 2546 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift) 2547 2548 /*define for DW_13 word*/ 2549 /*define for rect_z field*/ 2550 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_offset 13 2551 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask 0x000007FF 2552 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift 0 2553 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift) 2554 2555 /*define for linear_sw field*/ 2556 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_offset 13 2557 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask 0x00000003 2558 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift 16 2559 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift) 2560 2561 /*define for tile_sw field*/ 2562 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_offset 13 2563 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask 0x00000003 2564 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift 24 2565 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift) 2566 2567 2568 /* 2569 ** Definitions for SDMA_PKT_COPY_STRUCT packet 2570 */ 2571 2572 /*define for HEADER word*/ 2573 /*define for op field*/ 2574 #define SDMA_PKT_COPY_STRUCT_HEADER_op_offset 0 2575 #define SDMA_PKT_COPY_STRUCT_HEADER_op_mask 0x000000FF 2576 #define SDMA_PKT_COPY_STRUCT_HEADER_op_shift 0 2577 #define SDMA_PKT_COPY_STRUCT_HEADER_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_op_shift) 2578 2579 /*define for sub_op field*/ 2580 #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset 0 2581 #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask 0x000000FF 2582 #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift 8 2583 #define SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift) 2584 2585 /*define for tmz field*/ 2586 #define SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset 0 2587 #define SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask 0x00000001 2588 #define SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift 18 2589 #define SDMA_PKT_COPY_STRUCT_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask) << SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift) 2590 2591 /*define for detile field*/ 2592 #define SDMA_PKT_COPY_STRUCT_HEADER_detile_offset 0 2593 #define SDMA_PKT_COPY_STRUCT_HEADER_detile_mask 0x00000001 2594 #define SDMA_PKT_COPY_STRUCT_HEADER_detile_shift 31 2595 #define SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_detile_mask) << SDMA_PKT_COPY_STRUCT_HEADER_detile_shift) 2596 2597 /*define for SB_ADDR_LO word*/ 2598 /*define for sb_addr_31_0 field*/ 2599 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset 1 2600 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask 0xFFFFFFFF 2601 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift 0 2602 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift) 2603 2604 /*define for SB_ADDR_HI word*/ 2605 /*define for sb_addr_63_32 field*/ 2606 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset 2 2607 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask 0xFFFFFFFF 2608 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift 0 2609 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift) 2610 2611 /*define for START_INDEX word*/ 2612 /*define for start_index field*/ 2613 #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset 3 2614 #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask 0xFFFFFFFF 2615 #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift 0 2616 #define SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x) (((x) & SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask) << SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift) 2617 2618 /*define for COUNT word*/ 2619 /*define for count field*/ 2620 #define SDMA_PKT_COPY_STRUCT_COUNT_count_offset 4 2621 #define SDMA_PKT_COPY_STRUCT_COUNT_count_mask 0xFFFFFFFF 2622 #define SDMA_PKT_COPY_STRUCT_COUNT_count_shift 0 2623 #define SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_STRUCT_COUNT_count_mask) << SDMA_PKT_COPY_STRUCT_COUNT_count_shift) 2624 2625 /*define for DW_5 word*/ 2626 /*define for stride field*/ 2627 #define SDMA_PKT_COPY_STRUCT_DW_5_stride_offset 5 2628 #define SDMA_PKT_COPY_STRUCT_DW_5_stride_mask 0x000007FF 2629 #define SDMA_PKT_COPY_STRUCT_DW_5_stride_shift 0 2630 #define SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_stride_mask) << SDMA_PKT_COPY_STRUCT_DW_5_stride_shift) 2631 2632 /*define for linear_sw field*/ 2633 #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset 5 2634 #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask 0x00000003 2635 #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift 16 2636 #define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift) 2637 2638 /*define for struct_sw field*/ 2639 #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset 5 2640 #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask 0x00000003 2641 #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift 24 2642 #define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift) 2643 2644 /*define for LINEAR_ADDR_LO word*/ 2645 /*define for linear_addr_31_0 field*/ 2646 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset 6 2647 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 2648 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 2649 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift) 2650 2651 /*define for LINEAR_ADDR_HI word*/ 2652 /*define for linear_addr_63_32 field*/ 2653 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset 7 2654 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 2655 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 2656 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift) 2657 2658 2659 /* 2660 ** Definitions for SDMA_PKT_WRITE_UNTILED packet 2661 */ 2662 2663 /*define for HEADER word*/ 2664 /*define for op field*/ 2665 #define SDMA_PKT_WRITE_UNTILED_HEADER_op_offset 0 2666 #define SDMA_PKT_WRITE_UNTILED_HEADER_op_mask 0x000000FF 2667 #define SDMA_PKT_WRITE_UNTILED_HEADER_op_shift 0 2668 #define SDMA_PKT_WRITE_UNTILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_op_shift) 2669 2670 /*define for sub_op field*/ 2671 #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset 0 2672 #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask 0x000000FF 2673 #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift 8 2674 #define SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift) 2675 2676 /*define for encrypt field*/ 2677 #define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset 0 2678 #define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask 0x00000001 2679 #define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift 16 2680 #define SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift) 2681 2682 /*define for tmz field*/ 2683 #define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset 0 2684 #define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask 0x00000001 2685 #define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift 18 2686 #define SDMA_PKT_WRITE_UNTILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift) 2687 2688 /*define for DST_ADDR_LO word*/ 2689 /*define for dst_addr_31_0 field*/ 2690 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset 1 2691 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 2692 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift 0 2693 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift) 2694 2695 /*define for DST_ADDR_HI word*/ 2696 /*define for dst_addr_63_32 field*/ 2697 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset 2 2698 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 2699 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift 0 2700 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift) 2701 2702 /*define for DW_3 word*/ 2703 /*define for count field*/ 2704 #define SDMA_PKT_WRITE_UNTILED_DW_3_count_offset 3 2705 #define SDMA_PKT_WRITE_UNTILED_DW_3_count_mask 0x000FFFFF 2706 #define SDMA_PKT_WRITE_UNTILED_DW_3_count_shift 0 2707 #define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift) 2708 2709 /*define for sw field*/ 2710 #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset 3 2711 #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask 0x00000003 2712 #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift 24 2713 #define SDMA_PKT_WRITE_UNTILED_DW_3_SW(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift) 2714 2715 /*define for DATA0 word*/ 2716 /*define for data0 field*/ 2717 #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset 4 2718 #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask 0xFFFFFFFF 2719 #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift 0 2720 #define SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask) << SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift) 2721 2722 2723 /* 2724 ** Definitions for SDMA_PKT_WRITE_TILED packet 2725 */ 2726 2727 /*define for HEADER word*/ 2728 /*define for op field*/ 2729 #define SDMA_PKT_WRITE_TILED_HEADER_op_offset 0 2730 #define SDMA_PKT_WRITE_TILED_HEADER_op_mask 0x000000FF 2731 #define SDMA_PKT_WRITE_TILED_HEADER_op_shift 0 2732 #define SDMA_PKT_WRITE_TILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_op_shift) 2733 2734 /*define for sub_op field*/ 2735 #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset 0 2736 #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask 0x000000FF 2737 #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift 8 2738 #define SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift) 2739 2740 /*define for encrypt field*/ 2741 #define SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset 0 2742 #define SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask 0x00000001 2743 #define SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift 16 2744 #define SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift) 2745 2746 /*define for tmz field*/ 2747 #define SDMA_PKT_WRITE_TILED_HEADER_tmz_offset 0 2748 #define SDMA_PKT_WRITE_TILED_HEADER_tmz_mask 0x00000001 2749 #define SDMA_PKT_WRITE_TILED_HEADER_tmz_shift 18 2750 #define SDMA_PKT_WRITE_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_TILED_HEADER_tmz_shift) 2751 2752 /*define for DST_ADDR_LO word*/ 2753 /*define for dst_addr_31_0 field*/ 2754 #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset 1 2755 #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 2756 #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift 0 2757 #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift) 2758 2759 /*define for DST_ADDR_HI word*/ 2760 /*define for dst_addr_63_32 field*/ 2761 #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset 2 2762 #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 2763 #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift 0 2764 #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift) 2765 2766 /*define for DW_3 word*/ 2767 /*define for width field*/ 2768 #define SDMA_PKT_WRITE_TILED_DW_3_width_offset 3 2769 #define SDMA_PKT_WRITE_TILED_DW_3_width_mask 0x00003FFF 2770 #define SDMA_PKT_WRITE_TILED_DW_3_width_shift 0 2771 #define SDMA_PKT_WRITE_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_DW_3_width_shift) 2772 2773 /*define for DW_4 word*/ 2774 /*define for height field*/ 2775 #define SDMA_PKT_WRITE_TILED_DW_4_height_offset 4 2776 #define SDMA_PKT_WRITE_TILED_DW_4_height_mask 0x00003FFF 2777 #define SDMA_PKT_WRITE_TILED_DW_4_height_shift 0 2778 #define SDMA_PKT_WRITE_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_DW_4_height_shift) 2779 2780 /*define for depth field*/ 2781 #define SDMA_PKT_WRITE_TILED_DW_4_depth_offset 4 2782 #define SDMA_PKT_WRITE_TILED_DW_4_depth_mask 0x00001FFF 2783 #define SDMA_PKT_WRITE_TILED_DW_4_depth_shift 16 2784 #define SDMA_PKT_WRITE_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_DW_4_depth_shift) 2785 2786 /*define for DW_5 word*/ 2787 /*define for element_size field*/ 2788 #define SDMA_PKT_WRITE_TILED_DW_5_element_size_offset 5 2789 #define SDMA_PKT_WRITE_TILED_DW_5_element_size_mask 0x00000007 2790 #define SDMA_PKT_WRITE_TILED_DW_5_element_size_shift 0 2791 #define SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_element_size_shift) 2792 2793 /*define for swizzle_mode field*/ 2794 #define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset 5 2795 #define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask 0x0000001F 2796 #define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift 3 2797 #define SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift) 2798 2799 /*define for dimension field*/ 2800 #define SDMA_PKT_WRITE_TILED_DW_5_dimension_offset 5 2801 #define SDMA_PKT_WRITE_TILED_DW_5_dimension_mask 0x00000003 2802 #define SDMA_PKT_WRITE_TILED_DW_5_dimension_shift 9 2803 #define SDMA_PKT_WRITE_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_dimension_mask) << SDMA_PKT_WRITE_TILED_DW_5_dimension_shift) 2804 2805 /*define for mip_max field*/ 2806 #define SDMA_PKT_WRITE_TILED_DW_5_mip_max_offset 5 2807 #define SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask 0x0000000F 2808 #define SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift 16 2809 #define SDMA_PKT_WRITE_TILED_DW_5_MIP_MAX(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask) << SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift) 2810 2811 /*define for DW_6 word*/ 2812 /*define for x field*/ 2813 #define SDMA_PKT_WRITE_TILED_DW_6_x_offset 6 2814 #define SDMA_PKT_WRITE_TILED_DW_6_x_mask 0x00003FFF 2815 #define SDMA_PKT_WRITE_TILED_DW_6_x_shift 0 2816 #define SDMA_PKT_WRITE_TILED_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_DW_6_x_shift) 2817 2818 /*define for y field*/ 2819 #define SDMA_PKT_WRITE_TILED_DW_6_y_offset 6 2820 #define SDMA_PKT_WRITE_TILED_DW_6_y_mask 0x00003FFF 2821 #define SDMA_PKT_WRITE_TILED_DW_6_y_shift 16 2822 #define SDMA_PKT_WRITE_TILED_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_DW_6_y_shift) 2823 2824 /*define for DW_7 word*/ 2825 /*define for z field*/ 2826 #define SDMA_PKT_WRITE_TILED_DW_7_z_offset 7 2827 #define SDMA_PKT_WRITE_TILED_DW_7_z_mask 0x00001FFF 2828 #define SDMA_PKT_WRITE_TILED_DW_7_z_shift 0 2829 #define SDMA_PKT_WRITE_TILED_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_DW_7_z_shift) 2830 2831 /*define for sw field*/ 2832 #define SDMA_PKT_WRITE_TILED_DW_7_sw_offset 7 2833 #define SDMA_PKT_WRITE_TILED_DW_7_sw_mask 0x00000003 2834 #define SDMA_PKT_WRITE_TILED_DW_7_sw_shift 24 2835 #define SDMA_PKT_WRITE_TILED_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_DW_7_sw_shift) 2836 2837 /*define for COUNT word*/ 2838 /*define for count field*/ 2839 #define SDMA_PKT_WRITE_TILED_COUNT_count_offset 8 2840 #define SDMA_PKT_WRITE_TILED_COUNT_count_mask 0x000FFFFF 2841 #define SDMA_PKT_WRITE_TILED_COUNT_count_shift 0 2842 #define SDMA_PKT_WRITE_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_COUNT_count_shift) 2843 2844 /*define for DATA0 word*/ 2845 /*define for data0 field*/ 2846 #define SDMA_PKT_WRITE_TILED_DATA0_data0_offset 9 2847 #define SDMA_PKT_WRITE_TILED_DATA0_data0_mask 0xFFFFFFFF 2848 #define SDMA_PKT_WRITE_TILED_DATA0_data0_shift 0 2849 #define SDMA_PKT_WRITE_TILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_DATA0_data0_shift) 2850 2851 2852 /* 2853 ** Definitions for SDMA_PKT_WRITE_TILED_BC packet 2854 */ 2855 2856 /*define for HEADER word*/ 2857 /*define for op field*/ 2858 #define SDMA_PKT_WRITE_TILED_BC_HEADER_op_offset 0 2859 #define SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask 0x000000FF 2860 #define SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift 0 2861 #define SDMA_PKT_WRITE_TILED_BC_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift) 2862 2863 /*define for sub_op field*/ 2864 #define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_offset 0 2865 #define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask 0x000000FF 2866 #define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift 8 2867 #define SDMA_PKT_WRITE_TILED_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift) 2868 2869 /*define for DST_ADDR_LO word*/ 2870 /*define for dst_addr_31_0 field*/ 2871 #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_offset 1 2872 #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 2873 #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 2874 #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift) 2875 2876 /*define for DST_ADDR_HI word*/ 2877 /*define for dst_addr_63_32 field*/ 2878 #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_offset 2 2879 #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 2880 #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 2881 #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift) 2882 2883 /*define for DW_3 word*/ 2884 /*define for width field*/ 2885 #define SDMA_PKT_WRITE_TILED_BC_DW_3_width_offset 3 2886 #define SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask 0x00003FFF 2887 #define SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift 0 2888 #define SDMA_PKT_WRITE_TILED_BC_DW_3_WIDTH(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift) 2889 2890 /*define for DW_4 word*/ 2891 /*define for height field*/ 2892 #define SDMA_PKT_WRITE_TILED_BC_DW_4_height_offset 4 2893 #define SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask 0x00003FFF 2894 #define SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift 0 2895 #define SDMA_PKT_WRITE_TILED_BC_DW_4_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift) 2896 2897 /*define for depth field*/ 2898 #define SDMA_PKT_WRITE_TILED_BC_DW_4_depth_offset 4 2899 #define SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask 0x000007FF 2900 #define SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift 16 2901 #define SDMA_PKT_WRITE_TILED_BC_DW_4_DEPTH(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift) 2902 2903 /*define for DW_5 word*/ 2904 /*define for element_size field*/ 2905 #define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_offset 5 2906 #define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask 0x00000007 2907 #define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift 0 2908 #define SDMA_PKT_WRITE_TILED_BC_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift) 2909 2910 /*define for array_mode field*/ 2911 #define SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_offset 5 2912 #define SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask 0x0000000F 2913 #define SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift 3 2914 #define SDMA_PKT_WRITE_TILED_BC_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift) 2915 2916 /*define for mit_mode field*/ 2917 #define SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_offset 5 2918 #define SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask 0x00000007 2919 #define SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift 8 2920 #define SDMA_PKT_WRITE_TILED_BC_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift) 2921 2922 /*define for tilesplit_size field*/ 2923 #define SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_offset 5 2924 #define SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask 0x00000007 2925 #define SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift 11 2926 #define SDMA_PKT_WRITE_TILED_BC_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift) 2927 2928 /*define for bank_w field*/ 2929 #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_offset 5 2930 #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask 0x00000003 2931 #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift 15 2932 #define SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_W(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift) 2933 2934 /*define for bank_h field*/ 2935 #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_offset 5 2936 #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask 0x00000003 2937 #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift 18 2938 #define SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_H(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift) 2939 2940 /*define for num_bank field*/ 2941 #define SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_offset 5 2942 #define SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask 0x00000003 2943 #define SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift 21 2944 #define SDMA_PKT_WRITE_TILED_BC_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift) 2945 2946 /*define for mat_aspt field*/ 2947 #define SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_offset 5 2948 #define SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask 0x00000003 2949 #define SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift 24 2950 #define SDMA_PKT_WRITE_TILED_BC_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift) 2951 2952 /*define for pipe_config field*/ 2953 #define SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_offset 5 2954 #define SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask 0x0000001F 2955 #define SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift 26 2956 #define SDMA_PKT_WRITE_TILED_BC_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift) 2957 2958 /*define for DW_6 word*/ 2959 /*define for x field*/ 2960 #define SDMA_PKT_WRITE_TILED_BC_DW_6_x_offset 6 2961 #define SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask 0x00003FFF 2962 #define SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift 0 2963 #define SDMA_PKT_WRITE_TILED_BC_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift) 2964 2965 /*define for y field*/ 2966 #define SDMA_PKT_WRITE_TILED_BC_DW_6_y_offset 6 2967 #define SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask 0x00003FFF 2968 #define SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift 16 2969 #define SDMA_PKT_WRITE_TILED_BC_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift) 2970 2971 /*define for DW_7 word*/ 2972 /*define for z field*/ 2973 #define SDMA_PKT_WRITE_TILED_BC_DW_7_z_offset 7 2974 #define SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask 0x000007FF 2975 #define SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift 0 2976 #define SDMA_PKT_WRITE_TILED_BC_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift) 2977 2978 /*define for sw field*/ 2979 #define SDMA_PKT_WRITE_TILED_BC_DW_7_sw_offset 7 2980 #define SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask 0x00000003 2981 #define SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift 24 2982 #define SDMA_PKT_WRITE_TILED_BC_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift) 2983 2984 /*define for COUNT word*/ 2985 /*define for count field*/ 2986 #define SDMA_PKT_WRITE_TILED_BC_COUNT_count_offset 8 2987 #define SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask 0x000FFFFF 2988 #define SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift 2 2989 #define SDMA_PKT_WRITE_TILED_BC_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift) 2990 2991 /*define for DATA0 word*/ 2992 /*define for data0 field*/ 2993 #define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_offset 9 2994 #define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask 0xFFFFFFFF 2995 #define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift 0 2996 #define SDMA_PKT_WRITE_TILED_BC_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift) 2997 2998 2999 /* 3000 ** Definitions for SDMA_PKT_PTEPDE_COPY packet 3001 */ 3002 3003 /*define for HEADER word*/ 3004 /*define for op field*/ 3005 #define SDMA_PKT_PTEPDE_COPY_HEADER_op_offset 0 3006 #define SDMA_PKT_PTEPDE_COPY_HEADER_op_mask 0x000000FF 3007 #define SDMA_PKT_PTEPDE_COPY_HEADER_op_shift 0 3008 #define SDMA_PKT_PTEPDE_COPY_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_op_shift) 3009 3010 /*define for sub_op field*/ 3011 #define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset 0 3012 #define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask 0x000000FF 3013 #define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift 8 3014 #define SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift) 3015 3016 /*define for tmz field*/ 3017 #define SDMA_PKT_PTEPDE_COPY_HEADER_tmz_offset 0 3018 #define SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask 0x00000001 3019 #define SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift 18 3020 #define SDMA_PKT_PTEPDE_COPY_HEADER_TMZ(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift) 3021 3022 /*define for ptepde_op field*/ 3023 #define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset 0 3024 #define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask 0x00000001 3025 #define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift 31 3026 #define SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift) 3027 3028 /*define for SRC_ADDR_LO word*/ 3029 /*define for src_addr_31_0 field*/ 3030 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset 1 3031 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 3032 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift 0 3033 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift) 3034 3035 /*define for SRC_ADDR_HI word*/ 3036 /*define for src_addr_63_32 field*/ 3037 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset 2 3038 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 3039 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift 0 3040 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift) 3041 3042 /*define for DST_ADDR_LO word*/ 3043 /*define for dst_addr_31_0 field*/ 3044 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset 3 3045 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 3046 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift 0 3047 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift) 3048 3049 /*define for DST_ADDR_HI word*/ 3050 /*define for dst_addr_63_32 field*/ 3051 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset 4 3052 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 3053 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift 0 3054 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift) 3055 3056 /*define for MASK_DW0 word*/ 3057 /*define for mask_dw0 field*/ 3058 #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset 5 3059 #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask 0xFFFFFFFF 3060 #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift 0 3061 #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift) 3062 3063 /*define for MASK_DW1 word*/ 3064 /*define for mask_dw1 field*/ 3065 #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset 6 3066 #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask 0xFFFFFFFF 3067 #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift 0 3068 #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift) 3069 3070 /*define for COUNT word*/ 3071 /*define for count field*/ 3072 #define SDMA_PKT_PTEPDE_COPY_COUNT_count_offset 7 3073 #define SDMA_PKT_PTEPDE_COPY_COUNT_count_mask 0x0007FFFF 3074 #define SDMA_PKT_PTEPDE_COPY_COUNT_count_shift 0 3075 #define SDMA_PKT_PTEPDE_COPY_COUNT_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_count_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_count_shift) 3076 3077 3078 /* 3079 ** Definitions for SDMA_PKT_PTEPDE_COPY_BACKWARDS packet 3080 */ 3081 3082 /*define for HEADER word*/ 3083 /*define for op field*/ 3084 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset 0 3085 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask 0x000000FF 3086 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift 0 3087 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift) 3088 3089 /*define for sub_op field*/ 3090 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset 0 3091 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask 0x000000FF 3092 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift 8 3093 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift) 3094 3095 /*define for pte_size field*/ 3096 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset 0 3097 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask 0x00000003 3098 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift 28 3099 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift) 3100 3101 /*define for direction field*/ 3102 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset 0 3103 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask 0x00000001 3104 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift 30 3105 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift) 3106 3107 /*define for ptepde_op field*/ 3108 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset 0 3109 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask 0x00000001 3110 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift 31 3111 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift) 3112 3113 /*define for SRC_ADDR_LO word*/ 3114 /*define for src_addr_31_0 field*/ 3115 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset 1 3116 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 3117 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift 0 3118 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift) 3119 3120 /*define for SRC_ADDR_HI word*/ 3121 /*define for src_addr_63_32 field*/ 3122 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset 2 3123 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 3124 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift 0 3125 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift) 3126 3127 /*define for DST_ADDR_LO word*/ 3128 /*define for dst_addr_31_0 field*/ 3129 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset 3 3130 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 3131 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift 0 3132 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift) 3133 3134 /*define for DST_ADDR_HI word*/ 3135 /*define for dst_addr_63_32 field*/ 3136 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset 4 3137 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 3138 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift 0 3139 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift) 3140 3141 /*define for MASK_BIT_FOR_DW word*/ 3142 /*define for mask_first_xfer field*/ 3143 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset 5 3144 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask 0x000000FF 3145 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift 0 3146 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift) 3147 3148 /*define for mask_last_xfer field*/ 3149 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset 5 3150 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask 0x000000FF 3151 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift 8 3152 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift) 3153 3154 /*define for COUNT_IN_32B_XFER word*/ 3155 /*define for count field*/ 3156 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset 6 3157 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask 0x0001FFFF 3158 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift 0 3159 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift) 3160 3161 3162 /* 3163 ** Definitions for SDMA_PKT_PTEPDE_RMW packet 3164 */ 3165 3166 /*define for HEADER word*/ 3167 /*define for op field*/ 3168 #define SDMA_PKT_PTEPDE_RMW_HEADER_op_offset 0 3169 #define SDMA_PKT_PTEPDE_RMW_HEADER_op_mask 0x000000FF 3170 #define SDMA_PKT_PTEPDE_RMW_HEADER_op_shift 0 3171 #define SDMA_PKT_PTEPDE_RMW_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_op_shift) 3172 3173 /*define for sub_op field*/ 3174 #define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset 0 3175 #define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask 0x000000FF 3176 #define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift 8 3177 #define SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift) 3178 3179 /*define for mtype field*/ 3180 #define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_offset 0 3181 #define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask 0x00000007 3182 #define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift 16 3183 #define SDMA_PKT_PTEPDE_RMW_HEADER_MTYPE(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift) 3184 3185 /*define for gcc field*/ 3186 #define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset 0 3187 #define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask 0x00000001 3188 #define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift 19 3189 #define SDMA_PKT_PTEPDE_RMW_HEADER_GCC(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift) 3190 3191 /*define for sys field*/ 3192 #define SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset 0 3193 #define SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask 0x00000001 3194 #define SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift 20 3195 #define SDMA_PKT_PTEPDE_RMW_HEADER_SYS(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift) 3196 3197 /*define for snp field*/ 3198 #define SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset 0 3199 #define SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask 0x00000001 3200 #define SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift 22 3201 #define SDMA_PKT_PTEPDE_RMW_HEADER_SNP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift) 3202 3203 /*define for gpa field*/ 3204 #define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset 0 3205 #define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask 0x00000001 3206 #define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift 23 3207 #define SDMA_PKT_PTEPDE_RMW_HEADER_GPA(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift) 3208 3209 /*define for l2_policy field*/ 3210 #define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_offset 0 3211 #define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask 0x00000003 3212 #define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift 24 3213 #define SDMA_PKT_PTEPDE_RMW_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift) 3214 3215 /*define for ADDR_LO word*/ 3216 /*define for addr_31_0 field*/ 3217 #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset 1 3218 #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 3219 #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift 0 3220 #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift) 3221 3222 /*define for ADDR_HI word*/ 3223 /*define for addr_63_32 field*/ 3224 #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset 2 3225 #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 3226 #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift 0 3227 #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift) 3228 3229 /*define for MASK_LO word*/ 3230 /*define for mask_31_0 field*/ 3231 #define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset 3 3232 #define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask 0xFFFFFFFF 3233 #define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift 0 3234 #define SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask) << SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift) 3235 3236 /*define for MASK_HI word*/ 3237 /*define for mask_63_32 field*/ 3238 #define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset 4 3239 #define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask 0xFFFFFFFF 3240 #define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift 0 3241 #define SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask) << SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift) 3242 3243 /*define for VALUE_LO word*/ 3244 /*define for value_31_0 field*/ 3245 #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset 5 3246 #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask 0xFFFFFFFF 3247 #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift 0 3248 #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift) 3249 3250 /*define for VALUE_HI word*/ 3251 /*define for value_63_32 field*/ 3252 #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset 6 3253 #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask 0xFFFFFFFF 3254 #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift 0 3255 #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift) 3256 3257 3258 /* 3259 ** Definitions for SDMA_PKT_WRITE_INCR packet 3260 */ 3261 3262 /*define for HEADER word*/ 3263 /*define for op field*/ 3264 #define SDMA_PKT_WRITE_INCR_HEADER_op_offset 0 3265 #define SDMA_PKT_WRITE_INCR_HEADER_op_mask 0x000000FF 3266 #define SDMA_PKT_WRITE_INCR_HEADER_op_shift 0 3267 #define SDMA_PKT_WRITE_INCR_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_op_shift) 3268 3269 /*define for sub_op field*/ 3270 #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset 0 3271 #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask 0x000000FF 3272 #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift 8 3273 #define SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift) 3274 3275 /*define for DST_ADDR_LO word*/ 3276 /*define for dst_addr_31_0 field*/ 3277 #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset 1 3278 #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 3279 #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift 0 3280 #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift) 3281 3282 /*define for DST_ADDR_HI word*/ 3283 /*define for dst_addr_63_32 field*/ 3284 #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset 2 3285 #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 3286 #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift 0 3287 #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift) 3288 3289 /*define for MASK_DW0 word*/ 3290 /*define for mask_dw0 field*/ 3291 #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset 3 3292 #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask 0xFFFFFFFF 3293 #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift 0 3294 #define SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask) << SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift) 3295 3296 /*define for MASK_DW1 word*/ 3297 /*define for mask_dw1 field*/ 3298 #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset 4 3299 #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask 0xFFFFFFFF 3300 #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift 0 3301 #define SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask) << SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift) 3302 3303 /*define for INIT_DW0 word*/ 3304 /*define for init_dw0 field*/ 3305 #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset 5 3306 #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask 0xFFFFFFFF 3307 #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift 0 3308 #define SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask) << SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift) 3309 3310 /*define for INIT_DW1 word*/ 3311 /*define for init_dw1 field*/ 3312 #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset 6 3313 #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask 0xFFFFFFFF 3314 #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift 0 3315 #define SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask) << SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift) 3316 3317 /*define for INCR_DW0 word*/ 3318 /*define for incr_dw0 field*/ 3319 #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset 7 3320 #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask 0xFFFFFFFF 3321 #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift 0 3322 #define SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask) << SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift) 3323 3324 /*define for INCR_DW1 word*/ 3325 /*define for incr_dw1 field*/ 3326 #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset 8 3327 #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask 0xFFFFFFFF 3328 #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift 0 3329 #define SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask) << SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift) 3330 3331 /*define for COUNT word*/ 3332 /*define for count field*/ 3333 #define SDMA_PKT_WRITE_INCR_COUNT_count_offset 9 3334 #define SDMA_PKT_WRITE_INCR_COUNT_count_mask 0x0007FFFF 3335 #define SDMA_PKT_WRITE_INCR_COUNT_count_shift 0 3336 #define SDMA_PKT_WRITE_INCR_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_INCR_COUNT_count_mask) << SDMA_PKT_WRITE_INCR_COUNT_count_shift) 3337 3338 3339 /* 3340 ** Definitions for SDMA_PKT_INDIRECT packet 3341 */ 3342 3343 /*define for HEADER word*/ 3344 /*define for op field*/ 3345 #define SDMA_PKT_INDIRECT_HEADER_op_offset 0 3346 #define SDMA_PKT_INDIRECT_HEADER_op_mask 0x000000FF 3347 #define SDMA_PKT_INDIRECT_HEADER_op_shift 0 3348 #define SDMA_PKT_INDIRECT_HEADER_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_op_mask) << SDMA_PKT_INDIRECT_HEADER_op_shift) 3349 3350 /*define for sub_op field*/ 3351 #define SDMA_PKT_INDIRECT_HEADER_sub_op_offset 0 3352 #define SDMA_PKT_INDIRECT_HEADER_sub_op_mask 0x000000FF 3353 #define SDMA_PKT_INDIRECT_HEADER_sub_op_shift 8 3354 #define SDMA_PKT_INDIRECT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_sub_op_mask) << SDMA_PKT_INDIRECT_HEADER_sub_op_shift) 3355 3356 /*define for vmid field*/ 3357 #define SDMA_PKT_INDIRECT_HEADER_vmid_offset 0 3358 #define SDMA_PKT_INDIRECT_HEADER_vmid_mask 0x0000000F 3359 #define SDMA_PKT_INDIRECT_HEADER_vmid_shift 16 3360 #define SDMA_PKT_INDIRECT_HEADER_VMID(x) (((x) & SDMA_PKT_INDIRECT_HEADER_vmid_mask) << SDMA_PKT_INDIRECT_HEADER_vmid_shift) 3361 3362 /*define for priv field*/ 3363 #define SDMA_PKT_INDIRECT_HEADER_priv_offset 0 3364 #define SDMA_PKT_INDIRECT_HEADER_priv_mask 0x00000001 3365 #define SDMA_PKT_INDIRECT_HEADER_priv_shift 31 3366 #define SDMA_PKT_INDIRECT_HEADER_PRIV(x) (((x) & SDMA_PKT_INDIRECT_HEADER_priv_mask) << SDMA_PKT_INDIRECT_HEADER_priv_shift) 3367 3368 /*define for BASE_LO word*/ 3369 /*define for ib_base_31_0 field*/ 3370 #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset 1 3371 #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask 0xFFFFFFFF 3372 #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift 0 3373 #define SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x) (((x) & SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask) << SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift) 3374 3375 /*define for BASE_HI word*/ 3376 /*define for ib_base_63_32 field*/ 3377 #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset 2 3378 #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask 0xFFFFFFFF 3379 #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift 0 3380 #define SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x) (((x) & SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask) << SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift) 3381 3382 /*define for IB_SIZE word*/ 3383 /*define for ib_size field*/ 3384 #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset 3 3385 #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask 0x000FFFFF 3386 #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift 0 3387 #define SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x) (((x) & SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask) << SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift) 3388 3389 /*define for CSA_ADDR_LO word*/ 3390 /*define for csa_addr_31_0 field*/ 3391 #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset 4 3392 #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask 0xFFFFFFFF 3393 #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift 0 3394 #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift) 3395 3396 /*define for CSA_ADDR_HI word*/ 3397 /*define for csa_addr_63_32 field*/ 3398 #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset 5 3399 #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask 0xFFFFFFFF 3400 #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift 0 3401 #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift) 3402 3403 3404 /* 3405 ** Definitions for SDMA_PKT_SEMAPHORE packet 3406 */ 3407 3408 /*define for HEADER word*/ 3409 /*define for op field*/ 3410 #define SDMA_PKT_SEMAPHORE_HEADER_op_offset 0 3411 #define SDMA_PKT_SEMAPHORE_HEADER_op_mask 0x000000FF 3412 #define SDMA_PKT_SEMAPHORE_HEADER_op_shift 0 3413 #define SDMA_PKT_SEMAPHORE_HEADER_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_op_shift) 3414 3415 /*define for sub_op field*/ 3416 #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset 0 3417 #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask 0x000000FF 3418 #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift 8 3419 #define SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift) 3420 3421 /*define for write_one field*/ 3422 #define SDMA_PKT_SEMAPHORE_HEADER_write_one_offset 0 3423 #define SDMA_PKT_SEMAPHORE_HEADER_write_one_mask 0x00000001 3424 #define SDMA_PKT_SEMAPHORE_HEADER_write_one_shift 29 3425 #define SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_write_one_mask) << SDMA_PKT_SEMAPHORE_HEADER_write_one_shift) 3426 3427 /*define for signal field*/ 3428 #define SDMA_PKT_SEMAPHORE_HEADER_signal_offset 0 3429 #define SDMA_PKT_SEMAPHORE_HEADER_signal_mask 0x00000001 3430 #define SDMA_PKT_SEMAPHORE_HEADER_signal_shift 30 3431 #define SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_signal_mask) << SDMA_PKT_SEMAPHORE_HEADER_signal_shift) 3432 3433 /*define for mailbox field*/ 3434 #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset 0 3435 #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask 0x00000001 3436 #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift 31 3437 #define SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask) << SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift) 3438 3439 /*define for ADDR_LO word*/ 3440 /*define for addr_31_0 field*/ 3441 #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset 1 3442 #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 3443 #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift 0 3444 #define SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift) 3445 3446 /*define for ADDR_HI word*/ 3447 /*define for addr_63_32 field*/ 3448 #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset 2 3449 #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 3450 #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift 0 3451 #define SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift) 3452 3453 3454 /* 3455 ** Definitions for SDMA_PKT_FENCE packet 3456 */ 3457 3458 /*define for HEADER word*/ 3459 /*define for op field*/ 3460 #define SDMA_PKT_FENCE_HEADER_op_offset 0 3461 #define SDMA_PKT_FENCE_HEADER_op_mask 0x000000FF 3462 #define SDMA_PKT_FENCE_HEADER_op_shift 0 3463 #define SDMA_PKT_FENCE_HEADER_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_op_mask) << SDMA_PKT_FENCE_HEADER_op_shift) 3464 3465 /*define for sub_op field*/ 3466 #define SDMA_PKT_FENCE_HEADER_sub_op_offset 0 3467 #define SDMA_PKT_FENCE_HEADER_sub_op_mask 0x000000FF 3468 #define SDMA_PKT_FENCE_HEADER_sub_op_shift 8 3469 #define SDMA_PKT_FENCE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_sub_op_mask) << SDMA_PKT_FENCE_HEADER_sub_op_shift) 3470 3471 /*define for mtype field*/ 3472 #define SDMA_PKT_FENCE_HEADER_mtype_offset 0 3473 #define SDMA_PKT_FENCE_HEADER_mtype_mask 0x00000007 3474 #define SDMA_PKT_FENCE_HEADER_mtype_shift 16 3475 #define SDMA_PKT_FENCE_HEADER_MTYPE(x) (((x) & SDMA_PKT_FENCE_HEADER_mtype_mask) << SDMA_PKT_FENCE_HEADER_mtype_shift) 3476 3477 /*define for gcc field*/ 3478 #define SDMA_PKT_FENCE_HEADER_gcc_offset 0 3479 #define SDMA_PKT_FENCE_HEADER_gcc_mask 0x00000001 3480 #define SDMA_PKT_FENCE_HEADER_gcc_shift 19 3481 #define SDMA_PKT_FENCE_HEADER_GCC(x) (((x) & SDMA_PKT_FENCE_HEADER_gcc_mask) << SDMA_PKT_FENCE_HEADER_gcc_shift) 3482 3483 /*define for sys field*/ 3484 #define SDMA_PKT_FENCE_HEADER_sys_offset 0 3485 #define SDMA_PKT_FENCE_HEADER_sys_mask 0x00000001 3486 #define SDMA_PKT_FENCE_HEADER_sys_shift 20 3487 #define SDMA_PKT_FENCE_HEADER_SYS(x) (((x) & SDMA_PKT_FENCE_HEADER_sys_mask) << SDMA_PKT_FENCE_HEADER_sys_shift) 3488 3489 /*define for snp field*/ 3490 #define SDMA_PKT_FENCE_HEADER_snp_offset 0 3491 #define SDMA_PKT_FENCE_HEADER_snp_mask 0x00000001 3492 #define SDMA_PKT_FENCE_HEADER_snp_shift 22 3493 #define SDMA_PKT_FENCE_HEADER_SNP(x) (((x) & SDMA_PKT_FENCE_HEADER_snp_mask) << SDMA_PKT_FENCE_HEADER_snp_shift) 3494 3495 /*define for gpa field*/ 3496 #define SDMA_PKT_FENCE_HEADER_gpa_offset 0 3497 #define SDMA_PKT_FENCE_HEADER_gpa_mask 0x00000001 3498 #define SDMA_PKT_FENCE_HEADER_gpa_shift 23 3499 #define SDMA_PKT_FENCE_HEADER_GPA(x) (((x) & SDMA_PKT_FENCE_HEADER_gpa_mask) << SDMA_PKT_FENCE_HEADER_gpa_shift) 3500 3501 /*define for l2_policy field*/ 3502 #define SDMA_PKT_FENCE_HEADER_l2_policy_offset 0 3503 #define SDMA_PKT_FENCE_HEADER_l2_policy_mask 0x00000003 3504 #define SDMA_PKT_FENCE_HEADER_l2_policy_shift 24 3505 #define SDMA_PKT_FENCE_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_FENCE_HEADER_l2_policy_mask) << SDMA_PKT_FENCE_HEADER_l2_policy_shift) 3506 3507 /*define for ADDR_LO word*/ 3508 /*define for addr_31_0 field*/ 3509 #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset 1 3510 #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 3511 #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift 0 3512 #define SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift) 3513 3514 /*define for ADDR_HI word*/ 3515 /*define for addr_63_32 field*/ 3516 #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset 2 3517 #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 3518 #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift 0 3519 #define SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift) 3520 3521 /*define for DATA word*/ 3522 /*define for data field*/ 3523 #define SDMA_PKT_FENCE_DATA_data_offset 3 3524 #define SDMA_PKT_FENCE_DATA_data_mask 0xFFFFFFFF 3525 #define SDMA_PKT_FENCE_DATA_data_shift 0 3526 #define SDMA_PKT_FENCE_DATA_DATA(x) (((x) & SDMA_PKT_FENCE_DATA_data_mask) << SDMA_PKT_FENCE_DATA_data_shift) 3527 3528 3529 /* 3530 ** Definitions for SDMA_PKT_SRBM_WRITE packet 3531 */ 3532 3533 /*define for HEADER word*/ 3534 /*define for op field*/ 3535 #define SDMA_PKT_SRBM_WRITE_HEADER_op_offset 0 3536 #define SDMA_PKT_SRBM_WRITE_HEADER_op_mask 0x000000FF 3537 #define SDMA_PKT_SRBM_WRITE_HEADER_op_shift 0 3538 #define SDMA_PKT_SRBM_WRITE_HEADER_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_op_shift) 3539 3540 /*define for sub_op field*/ 3541 #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset 0 3542 #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask 0x000000FF 3543 #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift 8 3544 #define SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift) 3545 3546 /*define for byte_en field*/ 3547 #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset 0 3548 #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask 0x0000000F 3549 #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift 28 3550 #define SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask) << SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift) 3551 3552 /*define for ADDR word*/ 3553 /*define for addr field*/ 3554 #define SDMA_PKT_SRBM_WRITE_ADDR_addr_offset 1 3555 #define SDMA_PKT_SRBM_WRITE_ADDR_addr_mask 0x0003FFFF 3556 #define SDMA_PKT_SRBM_WRITE_ADDR_addr_shift 0 3557 #define SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_addr_mask) << SDMA_PKT_SRBM_WRITE_ADDR_addr_shift) 3558 3559 /*define for apertureid field*/ 3560 #define SDMA_PKT_SRBM_WRITE_ADDR_apertureid_offset 1 3561 #define SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask 0x00000FFF 3562 #define SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift 20 3563 #define SDMA_PKT_SRBM_WRITE_ADDR_APERTUREID(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask) << SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift) 3564 3565 /*define for DATA word*/ 3566 /*define for data field*/ 3567 #define SDMA_PKT_SRBM_WRITE_DATA_data_offset 2 3568 #define SDMA_PKT_SRBM_WRITE_DATA_data_mask 0xFFFFFFFF 3569 #define SDMA_PKT_SRBM_WRITE_DATA_data_shift 0 3570 #define SDMA_PKT_SRBM_WRITE_DATA_DATA(x) (((x) & SDMA_PKT_SRBM_WRITE_DATA_data_mask) << SDMA_PKT_SRBM_WRITE_DATA_data_shift) 3571 3572 3573 /* 3574 ** Definitions for SDMA_PKT_PRE_EXE packet 3575 */ 3576 3577 /*define for HEADER word*/ 3578 /*define for op field*/ 3579 #define SDMA_PKT_PRE_EXE_HEADER_op_offset 0 3580 #define SDMA_PKT_PRE_EXE_HEADER_op_mask 0x000000FF 3581 #define SDMA_PKT_PRE_EXE_HEADER_op_shift 0 3582 #define SDMA_PKT_PRE_EXE_HEADER_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_op_mask) << SDMA_PKT_PRE_EXE_HEADER_op_shift) 3583 3584 /*define for sub_op field*/ 3585 #define SDMA_PKT_PRE_EXE_HEADER_sub_op_offset 0 3586 #define SDMA_PKT_PRE_EXE_HEADER_sub_op_mask 0x000000FF 3587 #define SDMA_PKT_PRE_EXE_HEADER_sub_op_shift 8 3588 #define SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_sub_op_mask) << SDMA_PKT_PRE_EXE_HEADER_sub_op_shift) 3589 3590 /*define for dev_sel field*/ 3591 #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset 0 3592 #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask 0x000000FF 3593 #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift 16 3594 #define SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask) << SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift) 3595 3596 /*define for EXEC_COUNT word*/ 3597 /*define for exec_count field*/ 3598 #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset 1 3599 #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF 3600 #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift 0 3601 #define SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift) 3602 3603 3604 /* 3605 ** Definitions for SDMA_PKT_COND_EXE packet 3606 */ 3607 3608 /*define for HEADER word*/ 3609 /*define for op field*/ 3610 #define SDMA_PKT_COND_EXE_HEADER_op_offset 0 3611 #define SDMA_PKT_COND_EXE_HEADER_op_mask 0x000000FF 3612 #define SDMA_PKT_COND_EXE_HEADER_op_shift 0 3613 #define SDMA_PKT_COND_EXE_HEADER_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_op_mask) << SDMA_PKT_COND_EXE_HEADER_op_shift) 3614 3615 /*define for sub_op field*/ 3616 #define SDMA_PKT_COND_EXE_HEADER_sub_op_offset 0 3617 #define SDMA_PKT_COND_EXE_HEADER_sub_op_mask 0x000000FF 3618 #define SDMA_PKT_COND_EXE_HEADER_sub_op_shift 8 3619 #define SDMA_PKT_COND_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_sub_op_mask) << SDMA_PKT_COND_EXE_HEADER_sub_op_shift) 3620 3621 /*define for ADDR_LO word*/ 3622 /*define for addr_31_0 field*/ 3623 #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset 1 3624 #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 3625 #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift 0 3626 #define SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift) 3627 3628 /*define for ADDR_HI word*/ 3629 /*define for addr_63_32 field*/ 3630 #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset 2 3631 #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 3632 #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift 0 3633 #define SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift) 3634 3635 /*define for REFERENCE word*/ 3636 /*define for reference field*/ 3637 #define SDMA_PKT_COND_EXE_REFERENCE_reference_offset 3 3638 #define SDMA_PKT_COND_EXE_REFERENCE_reference_mask 0xFFFFFFFF 3639 #define SDMA_PKT_COND_EXE_REFERENCE_reference_shift 0 3640 #define SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x) (((x) & SDMA_PKT_COND_EXE_REFERENCE_reference_mask) << SDMA_PKT_COND_EXE_REFERENCE_reference_shift) 3641 3642 /*define for EXEC_COUNT word*/ 3643 /*define for exec_count field*/ 3644 #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset 4 3645 #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF 3646 #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift 0 3647 #define SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift) 3648 3649 3650 /* 3651 ** Definitions for SDMA_PKT_CONSTANT_FILL packet 3652 */ 3653 3654 /*define for HEADER word*/ 3655 /*define for op field*/ 3656 #define SDMA_PKT_CONSTANT_FILL_HEADER_op_offset 0 3657 #define SDMA_PKT_CONSTANT_FILL_HEADER_op_mask 0x000000FF 3658 #define SDMA_PKT_CONSTANT_FILL_HEADER_op_shift 0 3659 #define SDMA_PKT_CONSTANT_FILL_HEADER_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_op_shift) 3660 3661 /*define for sub_op field*/ 3662 #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset 0 3663 #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask 0x000000FF 3664 #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift 8 3665 #define SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift) 3666 3667 /*define for sw field*/ 3668 #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset 0 3669 #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask 0x00000003 3670 #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift 16 3671 #define SDMA_PKT_CONSTANT_FILL_HEADER_SW(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift) 3672 3673 /*define for fillsize field*/ 3674 #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset 0 3675 #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask 0x00000003 3676 #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift 30 3677 #define SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift) 3678 3679 /*define for DST_ADDR_LO word*/ 3680 /*define for dst_addr_31_0 field*/ 3681 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset 1 3682 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 3683 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift 0 3684 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift) 3685 3686 /*define for DST_ADDR_HI word*/ 3687 /*define for dst_addr_63_32 field*/ 3688 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset 2 3689 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 3690 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift 0 3691 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift) 3692 3693 /*define for DATA word*/ 3694 /*define for src_data_31_0 field*/ 3695 #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset 3 3696 #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask 0xFFFFFFFF 3697 #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift 0 3698 #define SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift) 3699 3700 /*define for COUNT word*/ 3701 /*define for count field*/ 3702 #define SDMA_PKT_CONSTANT_FILL_COUNT_count_offset 4 3703 #define SDMA_PKT_CONSTANT_FILL_COUNT_count_mask 0x003FFFFF 3704 #define SDMA_PKT_CONSTANT_FILL_COUNT_count_shift 0 3705 #define SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x) (((x) & SDMA_PKT_CONSTANT_FILL_COUNT_count_mask) << SDMA_PKT_CONSTANT_FILL_COUNT_count_shift) 3706 3707 3708 /* 3709 ** Definitions for SDMA_PKT_DATA_FILL_MULTI packet 3710 */ 3711 3712 /*define for HEADER word*/ 3713 /*define for op field*/ 3714 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset 0 3715 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask 0x000000FF 3716 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift 0 3717 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift) 3718 3719 /*define for sub_op field*/ 3720 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset 0 3721 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask 0x000000FF 3722 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift 8 3723 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift) 3724 3725 /*define for memlog_clr field*/ 3726 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset 0 3727 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask 0x00000001 3728 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift 31 3729 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift) 3730 3731 /*define for BYTE_STRIDE word*/ 3732 /*define for byte_stride field*/ 3733 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset 1 3734 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask 0xFFFFFFFF 3735 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift 0 3736 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift) 3737 3738 /*define for DMA_COUNT word*/ 3739 /*define for dma_count field*/ 3740 #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset 2 3741 #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask 0xFFFFFFFF 3742 #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift 0 3743 #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask) << SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift) 3744 3745 /*define for DST_ADDR_LO word*/ 3746 /*define for dst_addr_31_0 field*/ 3747 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset 3 3748 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 3749 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift 0 3750 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift) 3751 3752 /*define for DST_ADDR_HI word*/ 3753 /*define for dst_addr_63_32 field*/ 3754 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset 4 3755 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 3756 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift 0 3757 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift) 3758 3759 /*define for BYTE_COUNT word*/ 3760 /*define for count field*/ 3761 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset 5 3762 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask 0x03FFFFFF 3763 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift 0 3764 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift) 3765 3766 3767 /* 3768 ** Definitions for SDMA_PKT_POLL_REGMEM packet 3769 */ 3770 3771 /*define for HEADER word*/ 3772 /*define for op field*/ 3773 #define SDMA_PKT_POLL_REGMEM_HEADER_op_offset 0 3774 #define SDMA_PKT_POLL_REGMEM_HEADER_op_mask 0x000000FF 3775 #define SDMA_PKT_POLL_REGMEM_HEADER_op_shift 0 3776 #define SDMA_PKT_POLL_REGMEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_op_shift) 3777 3778 /*define for sub_op field*/ 3779 #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset 0 3780 #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask 0x000000FF 3781 #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift 8 3782 #define SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift) 3783 3784 /*define for hdp_flush field*/ 3785 #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset 0 3786 #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask 0x00000001 3787 #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift 26 3788 #define SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask) << SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift) 3789 3790 /*define for func field*/ 3791 #define SDMA_PKT_POLL_REGMEM_HEADER_func_offset 0 3792 #define SDMA_PKT_POLL_REGMEM_HEADER_func_mask 0x00000007 3793 #define SDMA_PKT_POLL_REGMEM_HEADER_func_shift 28 3794 #define SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_func_mask) << SDMA_PKT_POLL_REGMEM_HEADER_func_shift) 3795 3796 /*define for mem_poll field*/ 3797 #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset 0 3798 #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask 0x00000001 3799 #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift 31 3800 #define SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask) << SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift) 3801 3802 /*define for ADDR_LO word*/ 3803 /*define for addr_31_0 field*/ 3804 #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset 1 3805 #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 3806 #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift 0 3807 #define SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift) 3808 3809 /*define for ADDR_HI word*/ 3810 /*define for addr_63_32 field*/ 3811 #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset 2 3812 #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 3813 #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift 0 3814 #define SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift) 3815 3816 /*define for VALUE word*/ 3817 /*define for value field*/ 3818 #define SDMA_PKT_POLL_REGMEM_VALUE_value_offset 3 3819 #define SDMA_PKT_POLL_REGMEM_VALUE_value_mask 0xFFFFFFFF 3820 #define SDMA_PKT_POLL_REGMEM_VALUE_value_shift 0 3821 #define SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x) (((x) & SDMA_PKT_POLL_REGMEM_VALUE_value_mask) << SDMA_PKT_POLL_REGMEM_VALUE_value_shift) 3822 3823 /*define for MASK word*/ 3824 /*define for mask field*/ 3825 #define SDMA_PKT_POLL_REGMEM_MASK_mask_offset 4 3826 #define SDMA_PKT_POLL_REGMEM_MASK_mask_mask 0xFFFFFFFF 3827 #define SDMA_PKT_POLL_REGMEM_MASK_mask_shift 0 3828 #define SDMA_PKT_POLL_REGMEM_MASK_MASK(x) (((x) & SDMA_PKT_POLL_REGMEM_MASK_mask_mask) << SDMA_PKT_POLL_REGMEM_MASK_mask_shift) 3829 3830 /*define for DW5 word*/ 3831 /*define for interval field*/ 3832 #define SDMA_PKT_POLL_REGMEM_DW5_interval_offset 5 3833 #define SDMA_PKT_POLL_REGMEM_DW5_interval_mask 0x0000FFFF 3834 #define SDMA_PKT_POLL_REGMEM_DW5_interval_shift 0 3835 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift) 3836 3837 /*define for retry_count field*/ 3838 #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset 5 3839 #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask 0x00000FFF 3840 #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift 16 3841 #define SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask) << SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift) 3842 3843 3844 /* 3845 ** Definitions for SDMA_PKT_POLL_REG_WRITE_MEM packet 3846 */ 3847 3848 /*define for HEADER word*/ 3849 /*define for op field*/ 3850 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset 0 3851 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask 0x000000FF 3852 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift 0 3853 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift) 3854 3855 /*define for sub_op field*/ 3856 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset 0 3857 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask 0x000000FF 3858 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift 8 3859 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift) 3860 3861 /*define for SRC_ADDR word*/ 3862 /*define for addr_31_2 field*/ 3863 #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset 1 3864 #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask 0x3FFFFFFF 3865 #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift 2 3866 #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift) 3867 3868 /*define for DST_ADDR_LO word*/ 3869 /*define for addr_31_0 field*/ 3870 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 2 3871 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 3872 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 0 3873 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) 3874 3875 /*define for DST_ADDR_HI word*/ 3876 /*define for addr_63_32 field*/ 3877 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 3 3878 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 3879 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 0 3880 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) 3881 3882 3883 /* 3884 ** Definitions for SDMA_PKT_POLL_DBIT_WRITE_MEM packet 3885 */ 3886 3887 /*define for HEADER word*/ 3888 /*define for op field*/ 3889 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset 0 3890 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask 0x000000FF 3891 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift 0 3892 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift) 3893 3894 /*define for sub_op field*/ 3895 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset 0 3896 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask 0x000000FF 3897 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift 8 3898 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift) 3899 3900 /*define for ea field*/ 3901 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset 0 3902 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask 0x00000003 3903 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift 16 3904 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift) 3905 3906 /*define for DST_ADDR_LO word*/ 3907 /*define for addr_31_0 field*/ 3908 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 1 3909 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 3910 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 0 3911 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) 3912 3913 /*define for DST_ADDR_HI word*/ 3914 /*define for addr_63_32 field*/ 3915 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 2 3916 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 3917 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 0 3918 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) 3919 3920 /*define for START_PAGE word*/ 3921 /*define for addr_31_4 field*/ 3922 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset 3 3923 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask 0x0FFFFFFF 3924 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift 4 3925 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift) 3926 3927 /*define for PAGE_NUM word*/ 3928 /*define for page_num_31_0 field*/ 3929 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset 4 3930 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask 0xFFFFFFFF 3931 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift 0 3932 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift) 3933 3934 3935 /* 3936 ** Definitions for SDMA_PKT_POLL_MEM_VERIFY packet 3937 */ 3938 3939 /*define for HEADER word*/ 3940 /*define for op field*/ 3941 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset 0 3942 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask 0x000000FF 3943 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift 0 3944 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift) 3945 3946 /*define for sub_op field*/ 3947 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset 0 3948 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask 0x000000FF 3949 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift 8 3950 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift) 3951 3952 /*define for mode field*/ 3953 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset 0 3954 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask 0x00000001 3955 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift 31 3956 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift) 3957 3958 /*define for PATTERN word*/ 3959 /*define for pattern field*/ 3960 #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset 1 3961 #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask 0xFFFFFFFF 3962 #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift 0 3963 #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask) << SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift) 3964 3965 /*define for CMP0_ADDR_START_LO word*/ 3966 /*define for cmp0_start_31_0 field*/ 3967 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset 2 3968 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask 0xFFFFFFFF 3969 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift 0 3970 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift) 3971 3972 /*define for CMP0_ADDR_START_HI word*/ 3973 /*define for cmp0_start_63_32 field*/ 3974 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset 3 3975 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask 0xFFFFFFFF 3976 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift 0 3977 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift) 3978 3979 /*define for CMP0_ADDR_END_LO word*/ 3980 /*define for cmp1_end_31_0 field*/ 3981 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_offset 4 3982 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask 0xFFFFFFFF 3983 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift 0 3984 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP1_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift) 3985 3986 /*define for CMP0_ADDR_END_HI word*/ 3987 /*define for cmp1_end_63_32 field*/ 3988 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_offset 5 3989 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask 0xFFFFFFFF 3990 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift 0 3991 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP1_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift) 3992 3993 /*define for CMP1_ADDR_START_LO word*/ 3994 /*define for cmp1_start_31_0 field*/ 3995 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset 6 3996 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask 0xFFFFFFFF 3997 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift 0 3998 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift) 3999 4000 /*define for CMP1_ADDR_START_HI word*/ 4001 /*define for cmp1_start_63_32 field*/ 4002 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset 7 4003 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask 0xFFFFFFFF 4004 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift 0 4005 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift) 4006 4007 /*define for CMP1_ADDR_END_LO word*/ 4008 /*define for cmp1_end_31_0 field*/ 4009 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset 8 4010 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask 0xFFFFFFFF 4011 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift 0 4012 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift) 4013 4014 /*define for CMP1_ADDR_END_HI word*/ 4015 /*define for cmp1_end_63_32 field*/ 4016 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset 9 4017 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask 0xFFFFFFFF 4018 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift 0 4019 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift) 4020 4021 /*define for REC_ADDR_LO word*/ 4022 /*define for rec_31_0 field*/ 4023 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset 10 4024 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask 0xFFFFFFFF 4025 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift 0 4026 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift) 4027 4028 /*define for REC_ADDR_HI word*/ 4029 /*define for rec_63_32 field*/ 4030 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset 11 4031 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask 0xFFFFFFFF 4032 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift 0 4033 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift) 4034 4035 /*define for RESERVED word*/ 4036 /*define for reserved field*/ 4037 #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset 12 4038 #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask 0xFFFFFFFF 4039 #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift 0 4040 #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask) << SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift) 4041 4042 4043 /* 4044 ** Definitions for SDMA_PKT_ATOMIC packet 4045 */ 4046 4047 /*define for HEADER word*/ 4048 /*define for op field*/ 4049 #define SDMA_PKT_ATOMIC_HEADER_op_offset 0 4050 #define SDMA_PKT_ATOMIC_HEADER_op_mask 0x000000FF 4051 #define SDMA_PKT_ATOMIC_HEADER_op_shift 0 4052 #define SDMA_PKT_ATOMIC_HEADER_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_op_mask) << SDMA_PKT_ATOMIC_HEADER_op_shift) 4053 4054 /*define for loop field*/ 4055 #define SDMA_PKT_ATOMIC_HEADER_loop_offset 0 4056 #define SDMA_PKT_ATOMIC_HEADER_loop_mask 0x00000001 4057 #define SDMA_PKT_ATOMIC_HEADER_loop_shift 16 4058 #define SDMA_PKT_ATOMIC_HEADER_LOOP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_loop_mask) << SDMA_PKT_ATOMIC_HEADER_loop_shift) 4059 4060 /*define for tmz field*/ 4061 #define SDMA_PKT_ATOMIC_HEADER_tmz_offset 0 4062 #define SDMA_PKT_ATOMIC_HEADER_tmz_mask 0x00000001 4063 #define SDMA_PKT_ATOMIC_HEADER_tmz_shift 18 4064 #define SDMA_PKT_ATOMIC_HEADER_TMZ(x) (((x) & SDMA_PKT_ATOMIC_HEADER_tmz_mask) << SDMA_PKT_ATOMIC_HEADER_tmz_shift) 4065 4066 /*define for atomic_op field*/ 4067 #define SDMA_PKT_ATOMIC_HEADER_atomic_op_offset 0 4068 #define SDMA_PKT_ATOMIC_HEADER_atomic_op_mask 0x0000007F 4069 #define SDMA_PKT_ATOMIC_HEADER_atomic_op_shift 25 4070 #define SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_atomic_op_mask) << SDMA_PKT_ATOMIC_HEADER_atomic_op_shift) 4071 4072 /*define for ADDR_LO word*/ 4073 /*define for addr_31_0 field*/ 4074 #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset 1 4075 #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 4076 #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift 0 4077 #define SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask) << SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift) 4078 4079 /*define for ADDR_HI word*/ 4080 /*define for addr_63_32 field*/ 4081 #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset 2 4082 #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 4083 #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift 0 4084 #define SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask) << SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift) 4085 4086 /*define for SRC_DATA_LO word*/ 4087 /*define for src_data_31_0 field*/ 4088 #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset 3 4089 #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask 0xFFFFFFFF 4090 #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift 0 4091 #define SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask) << SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift) 4092 4093 /*define for SRC_DATA_HI word*/ 4094 /*define for src_data_63_32 field*/ 4095 #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset 4 4096 #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask 0xFFFFFFFF 4097 #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift 0 4098 #define SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask) << SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift) 4099 4100 /*define for CMP_DATA_LO word*/ 4101 /*define for cmp_data_31_0 field*/ 4102 #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset 5 4103 #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask 0xFFFFFFFF 4104 #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift 0 4105 #define SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask) << SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift) 4106 4107 /*define for CMP_DATA_HI word*/ 4108 /*define for cmp_data_63_32 field*/ 4109 #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset 6 4110 #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask 0xFFFFFFFF 4111 #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift 0 4112 #define SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask) << SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift) 4113 4114 /*define for LOOP_INTERVAL word*/ 4115 /*define for loop_interval field*/ 4116 #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset 7 4117 #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask 0x00001FFF 4118 #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift 0 4119 #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x) (((x) & SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask) << SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift) 4120 4121 4122 /* 4123 ** Definitions for SDMA_PKT_TIMESTAMP_SET packet 4124 */ 4125 4126 /*define for HEADER word*/ 4127 /*define for op field*/ 4128 #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset 0 4129 #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask 0x000000FF 4130 #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift 0 4131 #define SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift) 4132 4133 /*define for sub_op field*/ 4134 #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset 0 4135 #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask 0x000000FF 4136 #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift 8 4137 #define SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift) 4138 4139 /*define for INIT_DATA_LO word*/ 4140 /*define for init_data_31_0 field*/ 4141 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset 1 4142 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask 0xFFFFFFFF 4143 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift 0 4144 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift) 4145 4146 /*define for INIT_DATA_HI word*/ 4147 /*define for init_data_63_32 field*/ 4148 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset 2 4149 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask 0xFFFFFFFF 4150 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift 0 4151 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift) 4152 4153 4154 /* 4155 ** Definitions for SDMA_PKT_TIMESTAMP_GET packet 4156 */ 4157 4158 /*define for HEADER word*/ 4159 /*define for op field*/ 4160 #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset 0 4161 #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask 0x000000FF 4162 #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift 0 4163 #define SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift) 4164 4165 /*define for sub_op field*/ 4166 #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset 0 4167 #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask 0x000000FF 4168 #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift 8 4169 #define SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift) 4170 4171 /*define for WRITE_ADDR_LO word*/ 4172 /*define for write_addr_31_3 field*/ 4173 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset 1 4174 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF 4175 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift 3 4176 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift) 4177 4178 /*define for WRITE_ADDR_HI word*/ 4179 /*define for write_addr_63_32 field*/ 4180 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset 2 4181 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF 4182 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift 0 4183 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift) 4184 4185 4186 /* 4187 ** Definitions for SDMA_PKT_TIMESTAMP_GET_GLOBAL packet 4188 */ 4189 4190 /*define for HEADER word*/ 4191 /*define for op field*/ 4192 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset 0 4193 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask 0x000000FF 4194 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift 0 4195 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift) 4196 4197 /*define for sub_op field*/ 4198 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset 0 4199 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask 0x000000FF 4200 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift 8 4201 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift) 4202 4203 /*define for WRITE_ADDR_LO word*/ 4204 /*define for write_addr_31_3 field*/ 4205 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset 1 4206 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF 4207 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift 3 4208 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift) 4209 4210 /*define for WRITE_ADDR_HI word*/ 4211 /*define for write_addr_63_32 field*/ 4212 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset 2 4213 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF 4214 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift 0 4215 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift) 4216 4217 4218 /* 4219 ** Definitions for SDMA_PKT_TRAP packet 4220 */ 4221 4222 /*define for HEADER word*/ 4223 /*define for op field*/ 4224 #define SDMA_PKT_TRAP_HEADER_op_offset 0 4225 #define SDMA_PKT_TRAP_HEADER_op_mask 0x000000FF 4226 #define SDMA_PKT_TRAP_HEADER_op_shift 0 4227 #define SDMA_PKT_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_op_mask) << SDMA_PKT_TRAP_HEADER_op_shift) 4228 4229 /*define for sub_op field*/ 4230 #define SDMA_PKT_TRAP_HEADER_sub_op_offset 0 4231 #define SDMA_PKT_TRAP_HEADER_sub_op_mask 0x000000FF 4232 #define SDMA_PKT_TRAP_HEADER_sub_op_shift 8 4233 #define SDMA_PKT_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_sub_op_mask) << SDMA_PKT_TRAP_HEADER_sub_op_shift) 4234 4235 /*define for INT_CONTEXT word*/ 4236 /*define for int_context field*/ 4237 #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset 1 4238 #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF 4239 #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift 0 4240 #define SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift) 4241 4242 4243 /* 4244 ** Definitions for SDMA_PKT_DUMMY_TRAP packet 4245 */ 4246 4247 /*define for HEADER word*/ 4248 /*define for op field*/ 4249 #define SDMA_PKT_DUMMY_TRAP_HEADER_op_offset 0 4250 #define SDMA_PKT_DUMMY_TRAP_HEADER_op_mask 0x000000FF 4251 #define SDMA_PKT_DUMMY_TRAP_HEADER_op_shift 0 4252 #define SDMA_PKT_DUMMY_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_op_shift) 4253 4254 /*define for sub_op field*/ 4255 #define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset 0 4256 #define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask 0x000000FF 4257 #define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift 8 4258 #define SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift) 4259 4260 /*define for INT_CONTEXT word*/ 4261 /*define for int_context field*/ 4262 #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset 1 4263 #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF 4264 #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift 0 4265 #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift) 4266 4267 4268 /* 4269 ** Definitions for SDMA_PKT_GPUVM_INV packet 4270 */ 4271 4272 /*define for HEADER word*/ 4273 /*define for op field*/ 4274 #define SDMA_PKT_GPUVM_INV_HEADER_op_offset 0 4275 #define SDMA_PKT_GPUVM_INV_HEADER_op_mask 0x000000FF 4276 #define SDMA_PKT_GPUVM_INV_HEADER_op_shift 0 4277 #define SDMA_PKT_GPUVM_INV_HEADER_OP(x) (((x) & SDMA_PKT_GPUVM_INV_HEADER_op_mask) << SDMA_PKT_GPUVM_INV_HEADER_op_shift) 4278 4279 /*define for sub_op field*/ 4280 #define SDMA_PKT_GPUVM_INV_HEADER_sub_op_offset 0 4281 #define SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask 0x000000FF 4282 #define SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift 8 4283 #define SDMA_PKT_GPUVM_INV_HEADER_SUB_OP(x) (((x) & SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask) << SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift) 4284 4285 /*define for PAYLOAD1 word*/ 4286 /*define for per_vmid_inv_req field*/ 4287 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_offset 1 4288 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask 0x0000FFFF 4289 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift 0 4290 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_PER_VMID_INV_REQ(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift) 4291 4292 /*define for flush_type field*/ 4293 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_offset 1 4294 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask 0x00000007 4295 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift 16 4296 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_FLUSH_TYPE(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift) 4297 4298 /*define for l2_ptes field*/ 4299 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_offset 1 4300 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask 0x00000001 4301 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift 19 4302 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PTES(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift) 4303 4304 /*define for l2_pde0 field*/ 4305 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_offset 1 4306 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask 0x00000001 4307 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift 20 4308 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE0(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift) 4309 4310 /*define for l2_pde1 field*/ 4311 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_offset 1 4312 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask 0x00000001 4313 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift 21 4314 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE1(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift) 4315 4316 /*define for l2_pde2 field*/ 4317 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_offset 1 4318 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask 0x00000001 4319 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift 22 4320 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE2(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift) 4321 4322 /*define for l1_ptes field*/ 4323 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_offset 1 4324 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask 0x00000001 4325 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift 23 4326 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_L1_PTES(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift) 4327 4328 /*define for clr_protection_fault_status_addr field*/ 4329 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_offset 1 4330 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask 0x00000001 4331 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift 24 4332 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_CLR_PROTECTION_FAULT_STATUS_ADDR(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift) 4333 4334 /*define for log_request field*/ 4335 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_offset 1 4336 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask 0x00000001 4337 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift 25 4338 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_LOG_REQUEST(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift) 4339 4340 /*define for four_kilobytes field*/ 4341 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_offset 1 4342 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask 0x00000001 4343 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift 26 4344 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_FOUR_KILOBYTES(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift) 4345 4346 /*define for PAYLOAD2 word*/ 4347 /*define for s field*/ 4348 #define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_offset 2 4349 #define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask 0x00000001 4350 #define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift 0 4351 #define SDMA_PKT_GPUVM_INV_PAYLOAD2_S(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift) 4352 4353 /*define for page_va_42_12 field*/ 4354 #define SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_offset 2 4355 #define SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask 0x7FFFFFFF 4356 #define SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift 1 4357 #define SDMA_PKT_GPUVM_INV_PAYLOAD2_PAGE_VA_42_12(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift) 4358 4359 /*define for PAYLOAD3 word*/ 4360 /*define for page_va_47_43 field*/ 4361 #define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_offset 3 4362 #define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask 0x0000003F 4363 #define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift 0 4364 #define SDMA_PKT_GPUVM_INV_PAYLOAD3_PAGE_VA_47_43(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift) 4365 4366 4367 /* 4368 ** Definitions for SDMA_PKT_GCR_REQ packet 4369 */ 4370 4371 /*define for HEADER word*/ 4372 /*define for op field*/ 4373 #define SDMA_PKT_GCR_REQ_HEADER_op_offset 0 4374 #define SDMA_PKT_GCR_REQ_HEADER_op_mask 0x000000FF 4375 #define SDMA_PKT_GCR_REQ_HEADER_op_shift 0 4376 #define SDMA_PKT_GCR_REQ_HEADER_OP(x) (((x) & SDMA_PKT_GCR_REQ_HEADER_op_mask) << SDMA_PKT_GCR_REQ_HEADER_op_shift) 4377 4378 /*define for sub_op field*/ 4379 #define SDMA_PKT_GCR_REQ_HEADER_sub_op_offset 0 4380 #define SDMA_PKT_GCR_REQ_HEADER_sub_op_mask 0x000000FF 4381 #define SDMA_PKT_GCR_REQ_HEADER_sub_op_shift 8 4382 #define SDMA_PKT_GCR_REQ_HEADER_SUB_OP(x) (((x) & SDMA_PKT_GCR_REQ_HEADER_sub_op_mask) << SDMA_PKT_GCR_REQ_HEADER_sub_op_shift) 4383 4384 /*define for PAYLOAD1 word*/ 4385 /*define for base_va_31_7 field*/ 4386 #define SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_offset 1 4387 #define SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask 0x01FFFFFF 4388 #define SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift 7 4389 #define SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask) << SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift) 4390 4391 /*define for PAYLOAD2 word*/ 4392 /*define for base_va_47_32 field*/ 4393 #define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_offset 2 4394 #define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask 0x0000FFFF 4395 #define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift 0 4396 #define SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask) << SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift) 4397 4398 /*define for gcr_control_15_0 field*/ 4399 #define SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_offset 2 4400 #define SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask 0x0000FFFF 4401 #define SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift 16 4402 #define SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask) << SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift) 4403 4404 /*define for PAYLOAD3 word*/ 4405 /*define for gcr_control_18_16 field*/ 4406 #define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_offset 3 4407 #define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask 0x00000007 4408 #define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift 0 4409 #define SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask) << SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift) 4410 4411 /*define for limit_va_31_7 field*/ 4412 #define SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_offset 3 4413 #define SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask 0x01FFFFFF 4414 #define SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift 7 4415 #define SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask) << SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift) 4416 4417 /*define for PAYLOAD4 word*/ 4418 /*define for limit_va_47_32 field*/ 4419 #define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_offset 4 4420 #define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask 0x0000FFFF 4421 #define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift 0 4422 #define SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask) << SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift) 4423 4424 /*define for vmid field*/ 4425 #define SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_offset 4 4426 #define SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask 0x0000000F 4427 #define SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift 24 4428 #define SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask) << SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift) 4429 4430 4431 /* 4432 ** Definitions for SDMA_PKT_NOP packet 4433 */ 4434 4435 /*define for HEADER word*/ 4436 /*define for op field*/ 4437 #define SDMA_PKT_NOP_HEADER_op_offset 0 4438 #define SDMA_PKT_NOP_HEADER_op_mask 0x000000FF 4439 #define SDMA_PKT_NOP_HEADER_op_shift 0 4440 #define SDMA_PKT_NOP_HEADER_OP(x) (((x) & SDMA_PKT_NOP_HEADER_op_mask) << SDMA_PKT_NOP_HEADER_op_shift) 4441 4442 /*define for sub_op field*/ 4443 #define SDMA_PKT_NOP_HEADER_sub_op_offset 0 4444 #define SDMA_PKT_NOP_HEADER_sub_op_mask 0x000000FF 4445 #define SDMA_PKT_NOP_HEADER_sub_op_shift 8 4446 #define SDMA_PKT_NOP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_NOP_HEADER_sub_op_mask) << SDMA_PKT_NOP_HEADER_sub_op_shift) 4447 4448 /*define for count field*/ 4449 #define SDMA_PKT_NOP_HEADER_count_offset 0 4450 #define SDMA_PKT_NOP_HEADER_count_mask 0x00003FFF 4451 #define SDMA_PKT_NOP_HEADER_count_shift 16 4452 #define SDMA_PKT_NOP_HEADER_COUNT(x) (((x) & SDMA_PKT_NOP_HEADER_count_mask) << SDMA_PKT_NOP_HEADER_count_shift) 4453 4454 /*define for DATA0 word*/ 4455 /*define for data0 field*/ 4456 #define SDMA_PKT_NOP_DATA0_data0_offset 1 4457 #define SDMA_PKT_NOP_DATA0_data0_mask 0xFFFFFFFF 4458 #define SDMA_PKT_NOP_DATA0_data0_shift 0 4459 #define SDMA_PKT_NOP_DATA0_DATA0(x) (((x) & SDMA_PKT_NOP_DATA0_data0_mask) << SDMA_PKT_NOP_DATA0_data0_shift) 4460 4461 4462 /* 4463 ** Definitions for SDMA_AQL_PKT_HEADER packet 4464 */ 4465 4466 /*define for HEADER word*/ 4467 /*define for format field*/ 4468 #define SDMA_AQL_PKT_HEADER_HEADER_format_offset 0 4469 #define SDMA_AQL_PKT_HEADER_HEADER_format_mask 0x000000FF 4470 #define SDMA_AQL_PKT_HEADER_HEADER_format_shift 0 4471 #define SDMA_AQL_PKT_HEADER_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_format_mask) << SDMA_AQL_PKT_HEADER_HEADER_format_shift) 4472 4473 /*define for barrier field*/ 4474 #define SDMA_AQL_PKT_HEADER_HEADER_barrier_offset 0 4475 #define SDMA_AQL_PKT_HEADER_HEADER_barrier_mask 0x00000001 4476 #define SDMA_AQL_PKT_HEADER_HEADER_barrier_shift 8 4477 #define SDMA_AQL_PKT_HEADER_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_barrier_mask) << SDMA_AQL_PKT_HEADER_HEADER_barrier_shift) 4478 4479 /*define for acquire_fence_scope field*/ 4480 #define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset 0 4481 #define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask 0x00000003 4482 #define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift 9 4483 #define SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift) 4484 4485 /*define for release_fence_scope field*/ 4486 #define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset 0 4487 #define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask 0x00000003 4488 #define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift 11 4489 #define SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift) 4490 4491 /*define for reserved field*/ 4492 #define SDMA_AQL_PKT_HEADER_HEADER_reserved_offset 0 4493 #define SDMA_AQL_PKT_HEADER_HEADER_reserved_mask 0x00000007 4494 #define SDMA_AQL_PKT_HEADER_HEADER_reserved_shift 13 4495 #define SDMA_AQL_PKT_HEADER_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_reserved_mask) << SDMA_AQL_PKT_HEADER_HEADER_reserved_shift) 4496 4497 /*define for op field*/ 4498 #define SDMA_AQL_PKT_HEADER_HEADER_op_offset 0 4499 #define SDMA_AQL_PKT_HEADER_HEADER_op_mask 0x0000000F 4500 #define SDMA_AQL_PKT_HEADER_HEADER_op_shift 16 4501 #define SDMA_AQL_PKT_HEADER_HEADER_OP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_op_mask) << SDMA_AQL_PKT_HEADER_HEADER_op_shift) 4502 4503 /*define for subop field*/ 4504 #define SDMA_AQL_PKT_HEADER_HEADER_subop_offset 0 4505 #define SDMA_AQL_PKT_HEADER_HEADER_subop_mask 0x00000007 4506 #define SDMA_AQL_PKT_HEADER_HEADER_subop_shift 20 4507 #define SDMA_AQL_PKT_HEADER_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_subop_mask) << SDMA_AQL_PKT_HEADER_HEADER_subop_shift) 4508 4509 4510 /* 4511 ** Definitions for SDMA_AQL_PKT_COPY_LINEAR packet 4512 */ 4513 4514 /*define for HEADER word*/ 4515 /*define for format field*/ 4516 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset 0 4517 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask 0x000000FF 4518 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift 0 4519 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift) 4520 4521 /*define for barrier field*/ 4522 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset 0 4523 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask 0x00000001 4524 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift 8 4525 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift) 4526 4527 /*define for acquire_fence_scope field*/ 4528 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset 0 4529 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask 0x00000003 4530 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift 9 4531 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift) 4532 4533 /*define for release_fence_scope field*/ 4534 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset 0 4535 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask 0x00000003 4536 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift 11 4537 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift) 4538 4539 /*define for reserved field*/ 4540 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset 0 4541 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask 0x00000007 4542 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift 13 4543 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift) 4544 4545 /*define for op field*/ 4546 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset 0 4547 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask 0x0000000F 4548 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift 16 4549 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift) 4550 4551 /*define for subop field*/ 4552 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset 0 4553 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask 0x00000007 4554 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift 20 4555 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift) 4556 4557 /*define for RESERVED_DW1 word*/ 4558 /*define for reserved_dw1 field*/ 4559 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset 1 4560 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF 4561 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift 0 4562 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift) 4563 4564 /*define for RETURN_ADDR_LO word*/ 4565 /*define for return_addr_31_0 field*/ 4566 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset 2 4567 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask 0xFFFFFFFF 4568 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift 0 4569 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift) 4570 4571 /*define for RETURN_ADDR_HI word*/ 4572 /*define for return_addr_63_32 field*/ 4573 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset 3 4574 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask 0xFFFFFFFF 4575 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift 0 4576 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift) 4577 4578 /*define for COUNT word*/ 4579 /*define for count field*/ 4580 #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset 4 4581 #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF 4582 #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift 0 4583 #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift) 4584 4585 /*define for PARAMETER word*/ 4586 /*define for dst_sw field*/ 4587 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 5 4588 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003 4589 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16 4590 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) 4591 4592 /*define for src_sw field*/ 4593 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 5 4594 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003 4595 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24 4596 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) 4597 4598 /*define for SRC_ADDR_LO word*/ 4599 /*define for src_addr_31_0 field*/ 4600 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 6 4601 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 4602 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 4603 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 4604 4605 /*define for SRC_ADDR_HI word*/ 4606 /*define for src_addr_63_32 field*/ 4607 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 7 4608 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 4609 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 4610 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 4611 4612 /*define for DST_ADDR_LO word*/ 4613 /*define for dst_addr_31_0 field*/ 4614 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 8 4615 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 4616 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 4617 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) 4618 4619 /*define for DST_ADDR_HI word*/ 4620 /*define for dst_addr_63_32 field*/ 4621 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 9 4622 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 4623 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 4624 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) 4625 4626 /*define for RESERVED_DW10 word*/ 4627 /*define for reserved_dw10 field*/ 4628 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset 10 4629 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask 0xFFFFFFFF 4630 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift 0 4631 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift) 4632 4633 /*define for RESERVED_DW11 word*/ 4634 /*define for reserved_dw11 field*/ 4635 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset 11 4636 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask 0xFFFFFFFF 4637 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift 0 4638 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift) 4639 4640 /*define for RESERVED_DW12 word*/ 4641 /*define for reserved_dw12 field*/ 4642 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset 12 4643 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask 0xFFFFFFFF 4644 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift 0 4645 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift) 4646 4647 /*define for RESERVED_DW13 word*/ 4648 /*define for reserved_dw13 field*/ 4649 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset 13 4650 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF 4651 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift 0 4652 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift) 4653 4654 /*define for COMPLETION_SIGNAL_LO word*/ 4655 /*define for completion_signal_31_0 field*/ 4656 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 14 4657 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF 4658 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 0 4659 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) 4660 4661 /*define for COMPLETION_SIGNAL_HI word*/ 4662 /*define for completion_signal_63_32 field*/ 4663 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 15 4664 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF 4665 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0 4666 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) 4667 4668 4669 /* 4670 ** Definitions for SDMA_AQL_PKT_BARRIER_OR packet 4671 */ 4672 4673 /*define for HEADER word*/ 4674 /*define for format field*/ 4675 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset 0 4676 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask 0x000000FF 4677 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift 0 4678 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift) 4679 4680 /*define for barrier field*/ 4681 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset 0 4682 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask 0x00000001 4683 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift 8 4684 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift) 4685 4686 /*define for acquire_fence_scope field*/ 4687 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset 0 4688 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask 0x00000003 4689 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift 9 4690 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift) 4691 4692 /*define for release_fence_scope field*/ 4693 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset 0 4694 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask 0x00000003 4695 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift 11 4696 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift) 4697 4698 /*define for reserved field*/ 4699 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset 0 4700 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask 0x00000007 4701 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift 13 4702 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift) 4703 4704 /*define for op field*/ 4705 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset 0 4706 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask 0x0000000F 4707 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift 16 4708 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift) 4709 4710 /*define for subop field*/ 4711 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset 0 4712 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask 0x00000007 4713 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift 20 4714 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift) 4715 4716 /*define for RESERVED_DW1 word*/ 4717 /*define for reserved_dw1 field*/ 4718 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset 1 4719 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF 4720 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift 0 4721 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift) 4722 4723 /*define for DEPENDENT_ADDR_0_LO word*/ 4724 /*define for dependent_addr_0_31_0 field*/ 4725 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset 2 4726 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask 0xFFFFFFFF 4727 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift 0 4728 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift) 4729 4730 /*define for DEPENDENT_ADDR_0_HI word*/ 4731 /*define for dependent_addr_0_63_32 field*/ 4732 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset 3 4733 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask 0xFFFFFFFF 4734 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift 0 4735 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift) 4736 4737 /*define for DEPENDENT_ADDR_1_LO word*/ 4738 /*define for dependent_addr_1_31_0 field*/ 4739 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset 4 4740 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask 0xFFFFFFFF 4741 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift 0 4742 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift) 4743 4744 /*define for DEPENDENT_ADDR_1_HI word*/ 4745 /*define for dependent_addr_1_63_32 field*/ 4746 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset 5 4747 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask 0xFFFFFFFF 4748 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift 0 4749 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift) 4750 4751 /*define for DEPENDENT_ADDR_2_LO word*/ 4752 /*define for dependent_addr_2_31_0 field*/ 4753 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset 6 4754 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask 0xFFFFFFFF 4755 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift 0 4756 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift) 4757 4758 /*define for DEPENDENT_ADDR_2_HI word*/ 4759 /*define for dependent_addr_2_63_32 field*/ 4760 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset 7 4761 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask 0xFFFFFFFF 4762 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift 0 4763 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift) 4764 4765 /*define for DEPENDENT_ADDR_3_LO word*/ 4766 /*define for dependent_addr_3_31_0 field*/ 4767 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset 8 4768 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask 0xFFFFFFFF 4769 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift 0 4770 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift) 4771 4772 /*define for DEPENDENT_ADDR_3_HI word*/ 4773 /*define for dependent_addr_3_63_32 field*/ 4774 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset 9 4775 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask 0xFFFFFFFF 4776 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift 0 4777 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift) 4778 4779 /*define for DEPENDENT_ADDR_4_LO word*/ 4780 /*define for dependent_addr_4_31_0 field*/ 4781 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset 10 4782 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask 0xFFFFFFFF 4783 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift 0 4784 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift) 4785 4786 /*define for DEPENDENT_ADDR_4_HI word*/ 4787 /*define for dependent_addr_4_63_32 field*/ 4788 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset 11 4789 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask 0xFFFFFFFF 4790 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift 0 4791 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift) 4792 4793 /*define for RESERVED_DW12 word*/ 4794 /*define for reserved_dw12 field*/ 4795 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_offset 12 4796 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask 0xFFFFFFFF 4797 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift 0 4798 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_RESERVED_DW12(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift) 4799 4800 /*define for RESERVED_DW13 word*/ 4801 /*define for reserved_dw13 field*/ 4802 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset 13 4803 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF 4804 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift 0 4805 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift) 4806 4807 /*define for COMPLETION_SIGNAL_LO word*/ 4808 /*define for completion_signal_31_0 field*/ 4809 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 14 4810 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF 4811 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 0 4812 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) 4813 4814 /*define for COMPLETION_SIGNAL_HI word*/ 4815 /*define for completion_signal_63_32 field*/ 4816 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 15 4817 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF 4818 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0 4819 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) 4820 4821 4822 #endif /* __NAVI10_SDMA_PKT_OPEN_H_ */ 4823