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Searched refs:SH_MEM_CONFIG (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/radeon/
Dcik_sdma.c971 radeon_ring_write(ring, SH_MEM_CONFIG >> 2); in cik_dma_vm_flush()
Dcikd.h1171 #define SH_MEM_CONFIG 0x8C34 macro
Dcik.c5517 WREG32(SH_MEM_CONFIG, SH_MEM_CONFIG_GFX_DEFAULT); in cik_pcie_gart_enable()
/drivers/gpu/drm/amd/amdgpu/
Dgfx_v7_0.c1954 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, in gfx_v7_0_constants_init()
1956 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, DEFAULT_MTYPE, in gfx_v7_0_constants_init()
1958 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, APE1_MTYPE, in gfx_v7_0_constants_init()
1960 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, PRIVATE_ATC, 0); in gfx_v7_0_constants_init()
Dgfx_v8_0.c3795 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC); in gfx_v8_0_constants_init()
3796 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC); in gfx_v8_0_constants_init()
3797 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, in gfx_v8_0_constants_init()
3802 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC); in gfx_v8_0_constants_init()
3803 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC); in gfx_v8_0_constants_init()
3804 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, in gfx_v8_0_constants_init()
Dgfx_v9_0.c2585 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, in gfx_v9_0_constants_init()
2587 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, in gfx_v9_0_constants_init()
2592 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, in gfx_v9_0_constants_init()
2594 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, in gfx_v9_0_constants_init()