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Searched refs:SOR_DP_PADCTL_PAD_CAL_PD (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/tegra/
Dsor.h279 #define SOR_DP_PADCTL_PAD_CAL_PD (1 << 23) macro
Dsor.c766 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_dp_term_calibrate()
797 value |= SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_dp_term_calibrate()
2483 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_hdmi_enable()
2548 value |= SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_hdmi_enable()