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Searched refs:SOR_DP_PADCTL_PD_TXD (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/tegra/
Dsor.h292 #define SOR_DP_PADCTL_PD_TXD(x) (1 << (0 + (x))) macro
Dsor.c655 value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | in tegra_sor_power_up_lanes()
656 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2])); in tegra_sor_power_up_lanes()
658 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | in tegra_sor_power_up_lanes()
659 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]); in tegra_sor_power_up_lanes()
662 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); in tegra_sor_power_up_lanes()
664 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); in tegra_sor_power_up_lanes()
667 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); in tegra_sor_power_up_lanes()
669 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); in tegra_sor_power_up_lanes()