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Searched refs:SOR_DP_PADCTL_PD_TXD_0 (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/tegra/
Dsor.h289 #define SOR_DP_PADCTL_PD_TXD_0 (1 << 2) macro
Dsor.c701 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | in tegra_sor_power_down_lanes()
2315 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | in tegra_sor_hdmi_enable()