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Searched refs:SOR_LANE_SEQ_CTL_SEQUENCE_DOWN (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/tegra/
Dsor.h160 #define SOR_LANE_SEQ_CTL_SEQUENCE_DOWN (1 << 20) macro
Dsor.c674 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | in tegra_sor_power_up_lanes()
2327 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | in tegra_sor_hdmi_enable()