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Searched refs:SOR_PLL0_PLLREG_LEVEL (Results 1 – 1 of 1) sorted by relevance

/drivers/gpu/drm/tegra/
Dsor.h96 #define SOR_PLL0_PLLREG_LEVEL(x) (((x) & 0x3) << 6) macro
97 #define SOR_PLL0_PLLREG_LEVEL_V25 SOR_PLL0_PLLREG_LEVEL(0)
98 #define SOR_PLL0_PLLREG_LEVEL_V15 SOR_PLL0_PLLREG_LEVEL(1)
99 #define SOR_PLL0_PLLREG_LEVEL_V35 SOR_PLL0_PLLREG_LEVEL(2)
100 #define SOR_PLL0_PLLREG_LEVEL_V45 SOR_PLL0_PLLREG_LEVEL(3)