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Searched refs:SOR_PLL2_SEQ_PLLCAPPD (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/tegra/
Dsor.h121 #define SOR_PLL2_SEQ_PLLCAPPD (1 << 17) macro
Dsor.c1461 value |= SOR_PLL2_SEQ_PLLCAPPD; in tegra_sor_power_down()
2785 value |= SOR_PLL2_SEQ_PLLCAPPD; in tegra_sor_dp_enable()